sporkey 0 Posted September 5, 2016 Share Posted September 5, 2016 Hello, I was trying to setup 2 different PWM channels on my launchpad and noticed some strange behavior with timer1 using ACLK, and so I ran the following test, checking output of TA0CCR0 and TA1CCR0 on P1.1(TA0.0) and P2.0(TA1.0) with my oscilloscope. The only variables are P1SEL/P2SEL and TASSEL. Here's what I noticed: - Timer0 and timer1 both function properly with SMCLK, with different internal divider (and different CCR1s work as expected) - Timer1 cannot use ACLK at all. (output = low) - Timer0 with ACLK works properly alone. - Timer0 with ACLK doesn't work if port2 are selected for timer1 outputs. If timer1 uses SMCLK, timer1 works, but not timer0. If timer1 uses ACLK, both timer output = low. The outputs that confuse me are marked in RED in the table attached. Can someone please explain to me why timer1 with ACLK behaves that way? Am I overlooking anything in the datasheet? Thanks in advance. #include <msp430g2553.h> void clockConfig() { BCSCTL1 = CALBC1_1MHZ; // Set DCO DCOCTL = CALDCO_1MHZ; } void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT clockConfig(); P1OUT = BIT1; P1DIR = BIT1; P1SEL = BIT1; TACCR0 = 10; TACCTL0 = OUTMOD_4; TACTL = TASSEL_x | MC_1; P2OUT = BIT0 ; P2DIR = BIT0 ; P2SEL = BIT0; TA1CCR0 = 10; TA1CCTL0 = OUTMOD_4; TA1CTL = TASSEL_x | MC_1; } Hardware: EXP430G2 Rev 1.5 (MSP430G2553) Kit crystal installed with 12.5pf caps in C21/C22 oscilloscope Software: compiled with CCS 6.1.3 programmed with mspdebug Quote Link to post Share on other sites
roadrunner84 466 Posted September 6, 2016 Share Posted September 6, 2016 I think your problem is related to the crystal. The crystal is connected to P2.6 and P2.7, but you overwrite P2SEL and P2DIR with non-default values. As a result, the crystal is not controlled correctly anymore and ACLK is dead. To avoid this problem, try to use |= and &=~ as much as possible to set or clear bits. P1SEL |= BIT1; // set SEL1 bit 1 P1SEL &= ~BIT2; // clear SEL1 bit 2 P1SEL |= (BIT1 | BIT2); // set SEL1 bit 1 and 2 P1SEL &= ~(BIT1 | BIT2); // clear SEL1 bit 1 and 2 P1SEL = (P1SEL | BIT1) & ~BIT2; // set SEL1 bit 1 and clear bit 2 Fmilburn and sporkey 2 Quote Link to post Share on other sites
sporkey 0 Posted September 7, 2016 Author Share Posted September 7, 2016 Roadrunner, thanks so much! You are 100% correct. Great tips. Both ports function properly after changing P2SEL = BIT0 to P2SEL |= BIT0. To understand the problem a bit more, I tried messing with BIT6 at P2DIR and P2SEL. If I write P2DIR = BIT6; and P2SEL = BIT6;, it affects P1's use of ACLK. If I do P2DIR |= BIT6; and P2SEL |= BIT6;, P1's ACLK functions properly but P2 goes low. That is different from what I expected reading the datasheet. I thought that BIT6 at P2DIR/P2SEL turns XIN off and TA0.1 output on, but apparently it doesn't affect the crystal or turn it into TA0.1 output. Am I reading the datasheet wrong? Quote Link to post Share on other sites
roadrunner84 466 Posted September 8, 2016 Share Posted September 8, 2016 As I read the datasheet, after P2SEL = BIT6; P2.6 will be a timer output, but only if you write P2DIR = PIN6; too. So your crystal isn't oscillating anymore. If you write P2SEL |= BIT6; the crystal will be functioning because you set a bit that was already set. But if you add P2DIR |= BIT6; then you switch to an undescribed situation; it looks like you want the pin to behave like XOUT, not XIN. sporkey 1 Quote Link to post Share on other sites
sporkey 0 Posted September 8, 2016 Author Share Posted September 8, 2016 Thanks Roadrunner! I was deliberately trying to stop the crystal working to understand what got me in trouble earlier. I think I understand everything now. I did a bit more reading, and found the part I overlooked previously in the user Quote Link to post Share on other sites
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