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I bought two of the Hercules RM57L launchpads. I wonder why these aren't popular? At 330 mhz they could almost emulate an MSP430 and they look pretty classy.

Almost way too overpowered, and the dev environment is a bit unconventionally restrictive - you have to use HALCoGen to generate projects and CCS for the coding/building/debugging.  Not too bad for folks already comfy with the CCS toolchain et al, but it's still quite esoteric.  Probably 99% of hobbyist projects have no need for the power too... although there's a "Jan Cumps" on twitter from Belgium who's adopted the Hercules as his pet MCU of choice for giggles.


This is all mostly due to its "safety critical" nature, which shapes everything about how TI supports it.  TI's own TI-RTOS (aka SYS/BIOS aka DSP/BIOS) doesn't even support it, they include project generation for FreeRTOS for those who want an RTOS on the chip.  FreeRTOS does have safety critical "support" via their SafeRTOS variant.


OTOH the fact they have an all-in-one project generation tool that supports all the peripherals including the fascinating custom-VLIW instruction set "HET" timer is a bit envy-worthy; most TI MCUs just don't have such an "all in one" configurator.


Anyway I recommend you roll with it regardless!  There's probably a lot of cool stuff you can do with those with the right motivation.

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Off topic I suppose, and shows my background isn't EE, but why are MSP430s restricted to 16-25 MHz? Why aren't there 50 MHz MSP430s or faster?

I am guessing, but the ARM Cortex M0+ Instruction pipeline has two stages and seems a lot of devices clocked around 48MHz. The Cortex M3 and M4 have a three stage pipeline and 50-168MHz seems common.


The Cortex R7 has 11 pipeline stages to achieve very high clock frequencies. I would guess that the MSP430 has less pipelining potential due to being a low electrical power device.

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About the  'off topic' 16 / 25 MHz thing for MSP's:



Its likely more about marketing and silicon economics than physics or architectures, imho.

And likely no EE degree is needed on this one.


A possible scenario could be:


- MSPs are used in a defined market area of small machines, low cost, low performance demands, and likely high volume.

     (and there are a few other key drivers for the product certainly)


- 16MHz would cover a very large majority of the applications that an MSP would likely face in its market


- and 16 MHz is a pretty low speed for a modern CMOS chip process.....    This speed means, among other things, that the actual silicon chip size for an MSP is pretty small.     A higher speed would mean, again among other things, a bigger chip size in square millimeters.


- and that the process rules (line widths / parasitics) across the MSP line are reasonably fixed - ---   more variants = more differences from design to design  === a more difficult to control development environment for the TI MSP chip designers.  (thus, a 'bad' thing).

etcetera.   etcetera.  etcetera.


And finally - the point of it all - is that TI, or its fab partner, can make a huge number of MSP's per silicon wafer - a bigger number than for instance a faster / larger / higher-featured product.   A small chip, like the MSP, can have thousands per wafer, each wafer raw cost being 100's or so USD.     So, they strive for:  minimum chip die area / maximum yield thru conservative design / maximum working chips off a wafer.



So much of the chip industry is economics and it can become complex with lots of variables rather quickly.



Does that get close to the open / off-topic query?



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I'll politely advocate for the architectural constraints :) If TI committed to pipelining the MSP, they would most likely need to rework the variable length instruction set and break backwards/forwards compatibility. Adding pipelining overhead to the chip would also draw considerably more power from a chip sold as being a leader in low power. In the end, it's cheaper for TI to just buy an ARM license with a mature instruction set and architectural design and continue with higher frequency Cortex architectures. I think if ARM were not a more attractive option, there would be higher clocked pipelined MSPs hitting the market.

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There is the openmsp430 implemention on FPGA chips. Some seem to go to 100MHz




That does make sense though. FPGAs would use smaller feature sizes than a MSP430. IIRC MSP430 makes use of a large feature size primarily to achieve ultra-low leakage currents.

As you travel into some of these FPGAs the same (or reverse-engineered) logic chains will run faster than an IC with a larger feature size (increased capacitance, higher voltages, etc)


In fact the limiting factor is possibly a mixture of all the discussed points.



Weird. The opencores website is down at the moment.


I wonder what could be done with this?


OpenMSP is pretty cool, you can add instances of as many peripherals as you want. Or even make your own. I believe you loose all analog functionality though.

Of course FPGAs are also more expensive/larger than MSP430's

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