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monsonite

An Even Smaller MSP430FR2433 Dev Board

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Last week, I put together a design for a lightweight dev-board using the MSP4302433, known as "ChipStick".  ChipStick is a 20 pin DIL module that can plug into the socket on a G2 Launchpad.

 

In the week whilst waiting for the prototype boards to arrive, I have prototyped the design using a SMT adaptor - allowing it to be built on a breadboard.  Today I have refined the original concept, to produce a second design which, being small I have called Nanode (very small node).  

 

post-48241-0-22494000-1458430150_thumb.jpg

 

Nanode is effectively the same circuit as ChipStick, but trimmed to make a smaller form factor. The main difference is that it is pinned out to a 1.27mm pitch 2 x 10 pin connector - rather than the 2.54mm pitch DIL socket. I have also dispensed with the detachable programmer section.  "Where we're going Marty, we don't need programmers"

 

I have featured it on my  recent blogpost, 

 

http://sustburbia.blogspot.co.uk/2016/03/digital-dust-further-journey-into-nano.html

 

Once I have working examples, as usual I will make the design CAD files available.

 

 

 

Ken

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Spirilis,

 

I could have omitted one of the SPI memory devices, and put it on the back of the pcb - which would make it  even smaller - possibly even 0.3" x 0.3"  - but then you have the problem of getting the connections out sensibly.

 

As it stands its like a wide soic with 1.27mm (0.05") lead pitch - which in my book makes it now appear on the large size of what can effectively be soldered by hand.

 

As an interesting aside, the MSP430FR2433 seems to hand itself for being built into multi processor arrays.  The 3 comms ports  present themselves neatly on the west, south and east sides of the IC  - with the northside devoted to power, clock and SBW pins.

 

With a reduced footprint I am reasonably convinced that you could get a 10 x 10 array of these - plus memory onto a cheap 10 x 10 cm pcb.

 

But then you have the same old problem we have had since the transputer in the mid 1980s- how do you effectively co-ordinate and control a parallel array of processors. How do you allocate tasks across the array?

 

Steve Ciarcia did a Circuit Cellar (Byte Magazine) article in the late 1980s for a fractal computer - where he took 256 off  Intel 8748   microcontrollers and built them into an array .

 

Whilst Green Arrays can put 144 processor cores onto a single chip - I'm not sure that the world is beating a path to their door yet.  http://www.greenarraychips.com/

.

I have now been trying out   Jean Michel Thoorens "Fast Forth"   https://gitlab.com/Jean-Michel/FastForthForMSP430fr5xxx   which ports to most of the FRAM devices  including 'FR57xx, 'FR58xx, 'FR69xx

 

 
It uses a machine code implementation of Forth and  Uart communications at 921600 baud, so it that respect is pretty fast off the blocks.

 

 

 

 

Ken

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Spirilis,

 

I could have omitted one of the SPI memory devices, and put it on the back of the pcb - which would make it  even smaller - possibly even 0.3" x 0.3"  - but then you have the problem of getting the connections out sensibly.

 

As it stands its like a wide soic with 1.27mm (0.05") lead pitch - which in my book makes it now appear on the large size of what can effectively be soldered by hand.

 

As an interesting aside, the MSP430FR2433 seems to hand itself for being built into multi processor arrays.  The 3 comms ports  present themselves neatly on the west, south and east sides of the IC  - with the northside devoted to power, clock and SBW pins.

 

With a reduced footprint I am reasonably convinced that you could get a 10 x 10 array of these - plus memory onto a cheap 10 x 10 cm pcb.

 

But then you have the same old problem we have had since the transputer in the mid 1980s- how do you effectively co-ordinate and control a parallel array of processors. How do you allocate tasks across the array?

 

Steve Ciarcia did a Circuit Cellar (Byte Magazine) article in the late 1980s for a fractal computer - where he took 256 off  Intel 8748   microcontrollers and built them into an array .

 

Whilst Green Arrays can put 144 processor cores onto a single chip - I'm not sure that the world is beating a path to their door yet.  http://www.greenarraychips.com/

.

I have now been trying out   Jean Michel Thoorens "Fast Forth"   https://gitlab.com/Jean-Michel/FastForthForMSP430fr5xxx   which ports to most of the FRAM devices  including 'FR57xx, 'FR58xx, 'FR69xx

 

 
It uses a machine code implementation of Forth and  Uart communications at 921600 baud, so it that respect is pretty fast off the blocks.

 

 

 

 

Ken

That's cool!  Should see if any of the larger FR5xxx series devices have that sort of comms pinout... I've never used the QFN's myself.  Still somewhat skittish about trying lol.

 

I do love the FRAM for data storage though.

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Hi Spirilis,

 

Most of the FRAM parts have  2x USCI A and 1 x USCI B.

 

This allows you to use USCI A0 for your uart PC comms, USCI B0  for your SPI external memory  which leaves USCI A1 for communicating with any other device you wish.

 

Of course you can put multiple devices on a SPI bus - but I thought that to maintain memory bandwidth it was better to only put local memory devices on bus B.

 

In theory  - if you did have an array of these nano-processors - they could share memory devices - and as you only have 3 lines to handle - making a dual port memory from a serial device is fairly easy.

 

The memory cycle time is fairly slow  - about 3uS in streaming mode - but if you are interpreting some high level language like Forth, (particularly if it is written in machine code)  then the overhead to do an off-chip  fetch for the next Forth word is fairly low.    

 

The main point is the external memory gives you the flexibility to try these things - it's educational more than anything!

 

You could even use the external memory as a monochrome video store, or holding audio samples etc, etc.  For the sake of a $2 SRAM  - it  would be a shame not to have this fun extension.

 

 

 

Ken 

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It uses a machine code implementation of Forth and  Uart communications at 921600 baud, so it that respect is pretty fast off the blocks.

 

Most of the FRAM parts have  2x USCI A and 1 x USCI B.

 

This allows you to use USCI A0 for your uart PC comms, USCI B0  for your SPI external memory  which leaves USCI A1 for communicating with any other device you wish.

 

All FRAM devices are with mailbox system, so communication with PC can be done by existing SBW connection. It is fast, and all UART's are free. AFAIK it is not supported by TI FET's, but it is not big problem to made minimum SBW mailbox master device. My flasher use mailbox.

http://forum.43oh.com/topic/2972-sbw-msp430f550x-based-programmer/?p=54286

 

I use UART only for devices without mailbox support (2xx flash family), and UART at MSP430 can go over 1 Mbps without problems.

http://forum.43oh.com/topic/3413-msp430-uart-benchmark/

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Hi Jazz

 

Your UART benchmark tests are most useful - thanks for sharing    http://forum.43oh.com/topic/3413-msp430-uart-benchmark/

 

I found some interesting code by Rick Kimball - for low end  MSP430 equipped with USI   such as the the F2013 and the G2452

 

https://gist.github.com/RickKimball/1254043

 

By using software to add a start bit and stop bit to the output data of the USI shift register and setting the shift length to 10  - it is possible to transmit something that is like asynchronous uart data

 

Rick states that the baudrate will be the same as the USI clock - so that could be up to the 16MHz limit - giving a theoretical  16 Mbaud.   However most of the USB-Serial VCP devices such as CP2102, FT232 stop working at before 3Mbaud.

 

Has anyone experimented with high speed SPI. What is the maximum clock speed?   Is it possible to use extra GPIO lines to support QSPI or DSPI.  The 23LC1024 SPI SRAM has both QSPI and DSPI modes and it would be nice to have faster access if this could be done easily.

 

 

 

Ken

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I like the idea of the JTAG mailbox. @@jazz Does that mean I have to use a host side program to interface to jtag or can it be used like a normal cdc device?

 

I guess your solution implies use of your sbw+ jtag device.

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However most of the USB-Serial VCP devices such as CP2102, FT232 stop working at before 3Mbaud.

 

PL2303HXD can go up to 12 Mbps.

 

I like the idea of the JTAG mailbox. @@jazz Does that mean I have to use a host side program to interface to jtag or can it be used like a normal cdc device?

 

I guess your solution implies use of your sbw+ jtag device.

 

Master device mailbox (software) implementation is simple, because only few shiftings are used, for checking if there are data in target device mailbox, and flushing them. Mailbox operations are executed during target device free running mode (on any MCLK) and there is no need to put target device under JTAG / SBW control (get device) or to use any other JTAG / SBW function.

 

I was not thinking on my sbw+ flasher, but now I see that, for example TI FET with custom master mailbox solution will be limited. There must be some automatic switching, because only when SBW / JTAG (or BSL) bus is released from FET, mailbox master can use it.

 

My sbw+ flasher has 2 CDC / mailbox bridges that are active when CDC (mailbox) port is open and target devices are released from flasher (free running). Mailbox system is used from PC side as "normal" CDC device.

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