NJC 17 Posted December 11, 2015 Share Posted December 11, 2015 Hi everyone. I was looking through the Energia library (cores/msp430/twi.c) today trying to debug an issue I have been seeing, and noticed the following code: /* Work around for: * If the master does a read and then a write the START interrupt occurs * but the RX interrupt never fires. Clearing bit 4 and 5 of UCBxCTLW0 solves this. * bit 4 and 5 are however marked as reserved in the datasheet. */ UCBxCTLW0 &= ~0x18; Does anyone happen to know why this is? I have searched high and low for a reference on TI's forums and in their documentation to no avail. Thanks for the help! NJC Quote Link to post Share on other sites
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