Jump to content
Sign in to follow this  
NJC

I2C FRAM Stop Interrupt

Recommended Posts

Hi everyone. I was looking through the Energia library (cores/msp430/twi.c) today trying to debug an issue I have been seeing, and noticed the following code:

/* Work around for:
 * If the master does a read and then a write the START interrupt occurs
 * but the RX interrupt never fires. Clearing bit 4 and 5 of UCBxCTLW0 solves this.
 * bit 4 and 5 are however marked as reserved in the datasheet.
 */
UCBxCTLW0 &= ~0x18;

Does anyone happen to know why this is? I have searched high and low for a reference on TI's forums and in their documentation to no avail.

 

Thanks for the help!

 

NJC

Share this post


Link to post
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

Sign in to follow this  

×
×
  • Create New...