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Ambiq: game changer in Ultra Low Power?

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These scores suggest a real >2x performance breakthrough in low power consumption from Ambiq Micro's Apollo device:




I wonder if this technology is really ready for prime time and how the current industry leaders (TI, STM etc...) will respond/react... What do you think?


From the test notes it looks like the improvement in benchmark score is as much down to active mode current as sleep mode.


On the sleep mode side of things I think Ambiq are fortunate to have a sleep mode that includes exactly the features required for the EEMBC test. I think they're using the Deep Sleep + RTC mode, which is claimed at 198nA. Compare that with the MSP432 which uses LPM3 for the test at 850nA. MSP432 does have LPM4 at 25nA, but that has no RTC so can't be used in this case. The preliminary Apollo datasheet linked from EEMBC says the device has a shutdown mode which sounds very similar to LPM4, but unfortunately no specs are given.


The 34?A/MHz active power consumption claimed in the datasheet is impressive. Maybe that's down to the "Subthreshold Power Optimized Technology" mentioned in the datasheet. If that's the case I'd guess it would be difficult to match with current technologies. The big players might have new processes up their sleeve that will let them catch up, or maybe they'll just buy Ambiq out to get their IP. Ambiq was only founded in 2010, so probably still has VCs looking for a profitable exit...

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Looking at the specs though the hardware is lacking compared to most other MCUs on the market. a small assortment of Serial IO/s an ADC, and some timers. No DMA which means you actually need to wake up the processor to do stuff.

Also for these tests they have disabled half their flash and 7/8's of the RAM is powered down.


It does have impressive specs. But I would argue that in a final product. the average consumption would be more typical. Still very interesting

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I agree that an MCU is largely successful because of its peripherals, but we should also realize that this is their first shipping product. Regarding test optimizations I think those considerations apply to everyone and the possibility of shutting down parts of the SoC should be regarded as a feature (I believe TI has configurabile RAM in the MSP432 as well) and one of the pillars of ULP. The other interesting note is that their test was conducted using GCC while most others used commercial compilers, which could be better optimized.

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