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ISR Trap

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I'm running into a nasty problem and can't crawl my way out of it. While, I am fairly certain I have included interrupt service routines for all of the interrupts that I am using, the microcontroller still gets trapped under some mysterious interrupt: 

post-32777-0-65806800-1440853715_thumb.png

 

The trap triggers randomly, sometimes after a few minutes of running, sometimes several hours afterwards. I'm using CC430F5137 chip and below my isr.c handling the interrupts.

#include <stdint.h>
#include <stdio.h>

#include <msp430.h>
#include <cc430x513x.h>
#include "RF1A.h"
#include "hal.h"
#include "buffers.h"
#include "phy.h"

#ifdef _LL_
#include "ll.h"
#endif

/* whether to stay in the isr */
static uint8_t stayInISR = 0;

/*************************************************************************************
 * 								External variables 
 *************************************************************************************/
extern volatile uint8_t packetReceived;		//phy.c
extern volatile uint8_t packetTransmit;

extern uint8_t buttonPressed;		//hal.c
extern uint8_t enableUartLog;		//hal.c

uint8_t lqi;

/*************************************************************************************
 * 								MSP430 Core Interrupts
 *************************************************************************************/
#ifdef _LL_ /* _LL_ is predefined. This section is getting compiled */

/* Link Layer's timer */
#pragma vector=TIMER0_A0_VECTOR
__interrupt void Timer0_A0_ISR(void) {
	/* some magic */
}
#endif

#pragma vector=PORT1_VECTOR
__interrupt void PORT1_ISR(void) {
	switch(__even_in_range(P1IV, 16))
	{
	case  0: break;
	case  2: break;                         // P1.0 IFG
	case  4: 		                        // P1.1 IFG
		P1IFG &= ~BIT1;
		__delay_cycles(24000);				// 2ms debounce delay

		//button is active low
		if((P1IN & BIT1) == 0x00) {
			buttonPressed = 1;
		}
		__bic_SR_register_on_exit(LPM3_bits); 	//Exit active
		break;
	case  6: break;                         // P1.2 IFG
	case  8: break;                         // P1.3 IFG
	case 10: break;                         // P1.4 IFG
	case 12: break;                         // P1.5 IFG
	case 14: break;                         // P1.6 IFG
	case 16:                                // P1.7 IFG         
		break;
	}
}

#pragma vector=USCI_A0_VECTOR
__interrupt void USCI_A0_ISR(void)
{
	switch(__even_in_range(UCA0IV,4))
	{
	case 0:break;                             // Vector 0 - no interrupt
	case 2:                                   // Vector 2 - RXIFG
		while (!(UCA0IFG&UCTXIFG));             // USCI_A0 TX buffer ready?
		UCA0TXBUF = UCA0RXBUF;                  // TX -> RXed character
		break;
	case 4:break;                             // Vector 4 - TXIFG
	default: break;
	}
}

/* Application timer */
#pragma vector=TIMER1_A0_VECTOR
__interrupt void Timer1_ISR(void) {
	sendNow = 1;
	__bic_SR_register_on_exit(LPM3_bits);

}


/*************************************************************************************
 * 								MSP430 Core Unused interrupts
 *************************************************************************************/
#pragma vector=RTC_VECTOR
#pragma vector=PORT2_VECTOR
#pragma vector=AES_VECTOR  
#pragma vector=DMA_VECTOR
#pragma vector=ADC12_VECTOR 
#pragma vector=USCI_B0_VECTOR
#pragma vector=COMP_B_VECTOR 
__interrupt void Unused_Interrupt_ISR(void) {
	/* Real-time clock interrupts */
	RTCCTL0 &= ~(RTCRDYIE + RTCAIE);
	/* Port 2 interrupt */
	P2IE = 0;
	/* AES interrupt */
	AESACTL0 &= ~AESRDYIE;
	/* DMA interrupt */
	DMA0CTL &= ~DMAIE;
	DMA1CTL &= ~DMAIE;
	DMA2CTL &= ~DMAIE;
	/* ADC */
	ADC12IE = 0;
	/* USCI_B */
	UCB0IE = 0;
	/* Comparator B */
	CBINT = 0;
	
	while(stayInISR);
	
	__bic_SR_register_on_exit(LPM3);
}

/*************************************************************************************
 * 								RF Core Interrupts
 *************************************************************************************/
// Called if an interface error has occured. No interface errors should 
// exist in application code, so this is intended to be used for debugging
// or to catch errant operating conditions. 
static void RF1A_interface_error_handler(void)
{
	switch(__even_in_range(RF1AIFERRV,8))
	{
	case 0: break;                          // No error
	case 2:                                 // Low core voltage error     
		P1OUT &= ~BIT0;						// 00 = on LED's [D2,D1]
		P3OUT &= ~BIT6; 
		__no_operation();
		break; 
	case 4:                                 // Operand Error
		P1OUT |= BIT0;						// 01 = on LED's [D2,D1]
		P3OUT &= ~BIT6; 
		__no_operation();
		break;  
	case 6:                                 // Output data not available error 
		P1OUT &= ~BIT0;						// 10 = on LED's [D2,D1]
		P3OUT |= BIT6; 
		__no_operation();
		break;
	case 8:                                 // Operand overwrite error
		P1OUT |= BIT0;						// 11 = on LED's [D2,D1]
		P3OUT |= BIT6; 
		__no_operation();
		break; 
	}
}

// If RF1A_interrupt_handler is called, an interface interrupt has occured.
static void RF1A_interrupt_handler(void)
{
	// RF1A interrupt is pending
	switch(__even_in_range(RF1AIFIV,14))
	{
	case  0: break;                         // No interrupt pending
	case  2:                                // RFERRIFG 
		RF1A_interface_error_handler();
	case  4: break;                         // RFDOUTIFG
	case  6: break;                         // RFSTATIFG
	case  8: break;                         // RFDINIFG
	case 10: break;                         // RFINSTRIFG
	case 12: break;                         // RFRXIFG
	case 14: break;                         // RFTXIFG
	}
}

#pragma vector=CC1101_VECTOR
__interrupt void CC1101_ISR(void)
{
	switch(__even_in_range(RF1AIV,32))        // Prioritizing Radio Core Interrupts 
	{
	case  0:                                // No RF core interrupt pending                                            
		RF1A_interrupt_handler();             // means RF1A interface interrupt pending
		break; 
	case  2: break;                         // RFIFG0 
	case  4: break;                         // RFIFG1
	case  6: break;                         // RFIFG2
	case  8: break;                         // RFIFG3
	case 10:                                // RFIFG4 - RX end-of-packet
		packetReceived = 1;
		break;
	case 12: break;                         // RFIFG5
	case 14: break;                         // RFIFG6          
	case 16: break;                         // RFIFG7
	case 18: break;                         // RFIFG8
	case 20:                                // RFIFG9 - TX end-of-packet
		packetTransmit = 1;                   
		break;
	case 22: break;                         // RFIFG10
	case 24: break;                         // RFIFG11
	case 26: break;                         // RFIFG12
	case 28: break;                         // RFIFG13
	case 30: break;                         // RFIFG14
	case 32: break;                         // RFIFG15
	}  
	__bic_SR_register_on_exit(LPM3_bits);     
}
 

After the trap, the application just stops working, all the timers interrupt like Timer1_A0 ISR stops getting called altogether and the application layer halts. Am I missing any interrupts? How should I rewrite this file to make it look better/more organized?

 

Thanks for your help.

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