SMCLK and HardwareSerial

[SvdSinner 3]

I've got an F5229LP app that sets SMCLK to XT2 with a divider of 4. (XT2 = 25Mhz crystal, which is also the source for MCLK)

When I initialize the clocks, HardwareSerial no longer produces an accurate Baud Rate, and it breaks terminal communication.

I see that HardwareSerial.cpp contains:

#define SMCLK F_CPU //SMCLK = F_CPU for now

I've tried changing it to F_CPU / 4 but the situation did not improve.

 

Here is my recreation code:  (Uncomment initClocks(25000000l); and change HardwareSerial.cpp to see it fail)

#include <WString.h>
void initClocks(uint32_t mclkFreq);
void SerialTestText() {
	Serial.println("Back channel active.");
	char* selfTest = (char*) ("Performing Self Test.");
	while (*selfTest)
		Serial.print(*selfTest++);
	Serial.println(selfTest);
}

void setup() {
  // put your setup code here, to run once:
//	initClocks(25000000l);

	Serial.begin(115200);
	delay(10);

	//Turn on LED
	pinMode(RED_LED, OUTPUT);
	digitalWrite(RED_LED, true);
	Serial.println(' ');//Sacrificial character. (First character is often garbled.)
	SerialTestText();
}
int _previous = 0;
void loop() {
  // put your main code here, to run repeatedly: 
  int _now = millis()/2000;
  digitalWrite(RED_LED, (int)(millis()/500) & 0x1);
  if (_previous != _now)
	  SerialTestText();
  _previous = _now;
}

void initClocks(uint32_t mclkFreq) {
#ifdef __MSP430F5529__
	//Enable XT2
	P5SEL |= BIT3 + BIT2;
	UCSCTL6 &= ~XT2OFF;
	delay(100);  //Give time for XT2 to settle

	// Assign the XT1 as the FLL reference clock
	UCSCTL3 &= ~0x7;
	UCSCTL3 |= 0x2;//FLL reference clock divider of 1
	// Assign the XT2 as the MCLK reference clock
	UCSCTL4 &= ~0x7;//MCLK source bits
	UCSCTL4 |= 0x5;//Source = XT2 when available otherwise DCOCLKDIV
	UCSCTL5 &= ~0x7;//Clock divider of 1 (25Mhz)
	// Assign the XT2 as the SMCLK reference clock
	UCSCTL4 &= ~0x70;
	UCSCTL4 |= 0x50;//SMCLK
	UCSCTL5 &= ~0x70;
	UCSCTL5 |= 0x10; //Clock divider of 4 (6.25Mhz)
	// Assign the XT1 as the source for ACLK
	UCSCTL4 &= ~0x700;
	UCSCTL4 |= 0x100;//ACLK
	UCSCTL5 &= ~0x700;
	UCSCTL5 |= 0x100; //Clock divider of 16 (~4khz)
#endif
}

How do I use HardwareSerial with a custom value of SMCLK?

[roadrunner84 466]

Short answer: you can't.

 

Longer answer: The MSP430 has a few clocks running, most notable are ACLK and SMCLK, a third is MCLK, which is used to clock the CPU itself.

You cannot change the SMCLK value for the Hardware Serial, you can however set SMCLK to a different value. This is not related to HardwareSerial, it is related to the MSP430 clock system. In the family guide there is a chapter describing the clock system.

Note that things change when you alter SMCLK to run at a different divider or source, for example, delay functions may depend on ACLK or SMCLK to be a certain value. As a result, you may observe things like delay(100) waiting for 200ms.