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TI has two new Hercules LaunchPads

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Correct.    Only one interrupt request can be mapped to each channel.  But you could arrange the channels as you said in a group, linearly, so that all of the

I2C related interrupts in your example can easily be masked/unmasked in one operation.


The problem with that approach in general is that you cannot re-enable interrupts early. You have to either write a generic ISR shell that masks (and unmasks on return) the proper channels. This is 3 DWORDs you have to write. You also have to read based upon the channel number the mask you want to apply. 


Or you could generate proper ISR shell for each channel and use hardcoded values to mask & unmask.


So you are essentially introducing a long latency before you get to the very first useful instruction of your ISR.


But it's actually worse. Suppose you want to allow a ISR handler to enable/disable channels ? Then a hardcoded unmask will not work. You actually need to keep a softcopy of what is supposed to be enabled and restore that anded with the bits that you want to re-enable.



All I am saying is that it's a big pain, compared to NVIC or GIC. I always felt that exactly this, the better interrupt handling was a major plus for Cortex-R/Cortex-M over Cortex-A.


- Thomas

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