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Stellaris Launchpad: Write to flash during startup


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Hi all,

 

I need to write a bunch of values from SRAM to flash during the startup of the device. Thus, the code needs to be ASM and is part of Startup.s.

 

The TRM (page 487) states the following procedure to write to flash:

 

  1. Write source data to FMD register
  2. Write target address to FMA register
  3. write key and WRITE bit (0xA442001) to FMC register
  4. poll FMC register until the WRITE bit is cleared

 

I implemented the steps 1-3. However, there are several issues:

 

  1. How can I write the WRITEKEY and bit from step (3) to FMC? Using the key directly leads to a complaint:

Immediate 0x0A442001 cannot be represented by 0-255 shifted left by 0-23 or duplicated in all, odd or even bytes

 

     2. How do I implement step 4? I guess be loading the byte into a register and comparing it to value 1?

 

 

This is my code:

; UART2TestMain.s
; Runs on LM4F120 at 50 MHz
; Tests the UART0 to implement bidirectional data transfer to and from a
; computer running PuTTY.  This time, interrupts and FIFOs
; are used.
; This file is named "UART2" because it is the second UART example.
; It is not related to the UART2 module on the microcontroller.
; Daniel Valvano
; May 15, 2013

;  This example accompanies the book
;  "Embedded Systems: Real Time Interfacing to Arm Cortex M Microcontrollers",
;  ISBN: 978-1463590154, Jonathan Valvano, copyright (c) 2013
;  Program 5.11 Section 5.6, Program 3.10
;
;Copyright 2013 by Jonathan W. Valvano, valvano@mail.utexas.edu
;   You may use, edit, run or distribute this file
;   as long as the above copyright notice remains
;THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
;OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
;MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
;VALVANO SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
;OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
;For more information about my classes, my research, and my books, see
;http://users.ece.utexas.edu/~valvano/

; U0Rx (VCP receive) connected to PA0
; U0Tx (VCP transmit) connected to PA1

; standard ASCII symbols
CR                 EQU 0x0D
LF                 EQU 0x0A
BS                 EQU 0x08
ESC                EQU 0x1B
SPA                EQU 0x20
DEL                EQU 0x7F
UART0	EQU	0x10000001
ROM  	EQU	0x01000014
GPIOA	EQU	0x20000001
PCTLA	EQU	0x4000452C
UART0D  EQU	0x4000C000

FMA		EQU 0x400FD000
FMD		EQU 0x400FD004
FMC		EQU 0x400FD008
WRITEKEY	EQU 0xA4420000
WRITE_C		EQU	0x00000001

        AREA    DATA, ALIGN=2

        AREA    |.text|, CODE, READONLY, ALIGN=2
        THUMB
        EXPORT Start

    ALIGN                           ; make sure the end of this section is aligned


Start
		LDR		R5, =0x016FFFFF		; 0x016FFFFF ~ 4 sec, 0x00AFFFFF ~2 sec, 0x006FFFFF ~ 1 sec
		;LDR		R5, =0x00AFFFFF
		;LDR		R5, =0x006FFFFF

delay
		SUBS	R5, #1
		BNE		delay

startinit
		LDR     R0, =UART0
        LDR     R4, =ROM
        LDR     R5, [R4, #0x30]
        LDR     R6, [R5, #0x18]
        BLX     R6              	;Enable uart0
        LDR     R0, =GPIOA
        BLX     R6              	;Enable gpioA
        MOV.W   R0, #0x40004000 	;baseA
        MOVS    R1, #0x03       	;bit1 +bit0
        LDR     R6, [R4, #0x0C]
        LDR     R6, [R6, #0x54]
        BLX     R6              	;pin type
        LDR     R6, [R5, #0x60]
        BLX     R6              	;get clock frequency
        MOV     R1, R0
        LDR     R0, =UART0D
        MOV     R2, #115200
        MOV     R3, #0x60
        LDR     R5, [R4]
        MOV     R4, R0
        LDR     R6, [R5, #0x14]
        BLX     R6              	;115200, 8N1
        LDR     R6, [R5, #0x38]
        LDR     R5, [R5]
	MOV     R7, #0x8000     ; Size = Length (32K)
	MOV     R3, #0x20000000 ; Mem = RAM Address
	MOV	R11,#0x00001000	; Flash Address
	MOV	R12,#0			; Flash Offset
	LDR	R8, =FMD
	LDR	R9, =FMA
	LDR	R10,=FMC
main 
	LDRB    R1, [R3], #1
	STRB	R1, [R8]
	STRB	R11, [R9]
	MOV	R0, #0xA442001
	STR	R0, [R10]
		
	ADDS	R9, R9, #1	; Flash Offset++
	SUBS    R7, R7, #1      ; Size--
	BNE main
        END

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