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Initializing ADC0, jumps to Fault ISR


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Hello all,


I am stuck in initialization of the ADC, all that code used to work but now it just stopped working.This code is working fine in Keil IDE and also used to work in CCS.


I tried to debug the code and found at the following instruction it jumps to Fault ISR.


ADCSequenceDisable(ADC0_BASE, 0);


//ADC0_ACTSS_R &= ~(ADC_ACTSS_ASEN0); //Disable Sample Squencer0 before configuring it</span>I also tried to use the direct register access as mentioned above in commented text, but no luck.


The whole code of the program is;





int main(void)

{

    volatile unsigned int ulLoop;

    volatile unsigned long adcvalue;

    SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ);

 

    

    ulLoop = SYSCTL_RCGC2_R; //Some delay to stabilize the clock on the GPIO E and F modules

 

    initadc();

    

    adcvalue = readadc(AIN8); //PE5

 

    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);

    ulLoop = SYSCTL_RCGC2_R; //Some delay to stabilize the clock

    GPIO_PORTF_DIR_R |= 0x0EU; 

    GPIO_PORTF_DEN_R |= 0x0EU; 

    GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_1 | GPIO_PIN_2 |GPIO_PIN_3);

 

    while(1)

    {

        

        GPIO_PORTF_DATA_R = 0x00;

        

        GPIO_PORTF_DATA_R |= LED_RED;

        for(ulLoop = 0; ulLoop < 1800000; ulLoop++){ } // Delay

        GPIO_PORTF_DATA_R = 0x00;

 

        for(ulLoop = 0; ulLoop < 1800000; ulLoop++){ }

        GPIO_PORTF_DATA_R |= LED_GREEN;

        for(ulLoop = 0; ulLoop < 1800000; ulLoop++){ }

        GPIO_PORTF_DATA_R = 0x00;

 

        for(ulLoop = 0; ulLoop < 1800000; ulLoop++){ }

        GPIO_PORTF_DATA_R |= LED_BLUE;

        for(ulLoop = 0; ulLoop < 1800000; ulLoop++){ }

 

 

    }

 

 

}




and the initadc function is as follow;





#include "inc/hw_types.h"

#include "inc/lm4f120h5qr.h"

#include "driverlib/debug.h"

#include "driverlib/adc.h"

#include "inc/hw_memmap.h"

#include "driverlib/sysctl.h"

 

 

 

/*initadc() function initializes ADC0 and partially initializes Sample Sequencer 0. It doesnt assign the required adc channel pin.*/

 

void initadc(void)

{      

    volatile unsigned int ulLoop;

    

    

    //configuring ADC0 module

    SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);

    SysCtlADCSpeedSet(SYSCTL_ADCSPEED_250KSPS);

    ulLoop = SYSCTL_RCGC0_R; //Stabilize the clock

 

    //SYSCTL_RCGC0_R |= SYSCTL_RCGC0_ADC0SPD_250K; //Configure ADC0 to sample at 250kHz

    //SYSCTL_RCGC0_R |= SYSCTL_RCGC0_ADC0; //Enable clock to ADC0 Module

    

    //Configuring Sample Squencer 0

    ADCSequenceDisable(ADC0_BASE, 0);

    //ADC0_ACTSS_R &= ~(ADC_ACTSS_ASEN0); //Disable Sample Squencer0 before configuring it

    

    //Configuring Sample Squencer priorities

    ADCSequenceConfigure(ADC0_BASE, 0, ADC_TRIGGER_PROCESSOR, 0);

    //ADC0_SSPRI_R = (ADC_SSPRI_SS0_1ST | ADC_SSPRI_SS1_2ND | ADC_SSPRI_SS2_3RD | ADC_SSPRI_SS3_4TH);

    

    //Select Event triggering mode e.g Process triggered, Timer triggered, GPIO triggered etc

    //ADC0_EMUX_R = (ADC_EMUX_EM0_PROCESSOR); //Process triggered

    

    /*

    //Configuring the squence steps (i.e. assigning the adc channels (e.g. AIN0 is adc channel 0 = PE3 pin) that is to read)

    ADC0_SSMUX0_R &= ~(0x0000000F); //Clear MUX0 field

    //Here we can add multiple ADC channels by configuring ADCSSMUX0 register of SS0//

    ADC0_SSMUX0_R |= 0x00000001; //Select AIN1 i.e. PE2 as a first sample of the sample sequencer 0

    

    //Configuring sample sequencer 0 control

    //In case of more then one ADC channel used in SS0. END bit of ADCSSCTL0 register should be made active for the last sample//

    ADC0_SSCTL0_R =  ADC_SSCTL0_END0 | ADC_SSCTL0_IE0; //First sample is END of sampling and interupt is enabled on completing first sample

    

    //Enable the Sample Sequencer 0

    ADC0_ACTSS_R |= (ADC_ACTSS_ASEN0); */

    

 

         // Enable the GPIO Port E. PortE is used with AIN8 i.e. PE5 as ADC pin

            SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOE;

            ulLoop = SYSCTL_RCGC2_R; //Stabilize the clock

            GPIO_PORTE_DIR_R &= ~0x10;      // 2) make PE5 input

            GPIO_PORTE_AFSEL_R |= 0x10;     // 3) enable alternate function on PE5

            GPIO_PORTE_DEN_R &= ~0x10;      // 4) disable digital I/O on PE5

            GPIO_PORTE_AMSEL_R |= 0x10;     // 5) enable analog function on PE5

 

}

 

 

 

/*long readadc(int) partially initialized the Sample Squencer 0 and assigns the required adc channel pin*/

unsigned long readadc(unsigned int channel)

{

    volatile unsigned long result;

    

    ADC0_SSMUX0_R |= channel; //Select channel i.e. AINn i.e. PE2 as a first sample of the sample sequencer 0

    

    //Configuring sample sequencer 0 control

    //ADCSequenceStepConfigure(ADC0_BASE, 0, 0, ADC_CTL_TS | ADC_CTL_IE | ADC_CTL_END);

    //ADC0_SSCTL0_R =  ADC_SSCTL0_END0 | ADC_SSCTL0_IE0; //First sample is END of sampling and interupt is enabled on completing first sample

    //Enable the Sample Sequencer 0

    ADC0_ACTSS_R |= (ADC_ACTSS_ASEN0);

    

    //initiate SS0

    ADC0_PSSI_R = 0x01; //0x01=SS0, 0x02=SS1, 0x04=SS2, 0x08=SS3

    //Wait for interupt for SS0 conversion complete

    while((ADC0_RIS_R&0x01)==0)

        {//Do nothing

            }

    result = ADC0_SSFIFO0_R;       

    // Acknowlodgement the interupt for SS0

    ADC0_ISC_R |= 0x01;

            

    //Return the result

    return result;

    

}



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