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and again weird errors - Keil uVision


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I'd start by comparing the SPI and GPIO module register configurations in both programs, probably by dumping the register memory for the modules.

 

Also, looking at the analyzer traces the SPI clock in both versions looks odd (I'd expect 8 evenly-spaced pulses per octet transferred, with a slightly larger gap between octets). The ENABLE line is clearly wrong in your program: normally you'd see ENABLE low at any time when there's clock activity. (That it goes high again between octets in the Energia program is unusual but may be appropriate if the slave chip's interface operates on single-octet commands.)

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ENABLE is done using regular GPIO and I did not change the timing, I've just replaced digitalWrite() with GPIO_PORTA_DATA_R bit modifications. The clock jumped into my eye too but this is done by the SSI module. hmmmm....

 

Single step through the SPI read and write functions does not really work. CCS gives error messages 'unable to read memory address ...' and loosing connection to the debugger.

 

Thanks,

Stephan

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So, took a break and played a bit with a freescale FRDM board. And...wheeehee...progress ! :)

 

I wrote down the byte sequence sent at initialisation and checked back with the logic analyzer. I noticed there was an extra 0x00 after each byte.

unsigned char SPI_transfer(unsigned char data){
	unsigned char rec_data;

	GPIO_PORTA_DATA_R &= ~chipSelectPin;	// !CS = 0
	rec_data = sendAfterWaiting(data);	// send command
	// rec_data = sendAfterWaiting(0);	!!!	d'OH !!!	// send nothing, receive byte
	GPIO_PORTA_DATA_R |= chipSelectPin;	// !CS = 1

	return rec_data;
}

And then in the terminal window:

MFRC522 Version: 0x91

This looks good. It's still not reading tags but the SPI communication seems to be right now (Freescale mode, SPO=SPH=0)

 

 

post-3-14264605423476_thumb.png

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