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SSI and LM4F120XL

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Today i try next steps:

 

1. Switch off all other functions.

2. Reconnect and reconfigure to pins SSI0_BASE

3. Correct read function to                 SSIDataPut(OUR_SSI, ((addr<<1)&0x7E) | 0x80);

4. Change SSI speed to 4'000'000

5a. WIth SSI_FRF_MOTO_MODE_0

i receive

post-3079-14264605406091_thumb.jpg

5b. With SSI_FRF_MOTO_MODE_3

post-3079-1426460540639_thumb.jpg

post-3079-14264605406712_thumb.jpg

 

Result - have nothing :(

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Hi,

Seems the mode 3 is same as mode 0 - but mode 3 should show 16 consecutive clock pulses without pause, same the Enable signal - should not rise up between bytes - clearly you must modify something in your routine - this expression: while(SSIBusy(OUR_SSI)); should be eliminated - each function SSIDataPut waits inside for not busy, so no need for extra  waiting. Also, the transmission sequence should be SSIDataPut, SSIDataPut, SSIDataGet, SSIDataGet - also the *Get function is with waiting. This apply also for mode 0. What is OUR_SSI? (is it SSI3 or not?)

 

Check also the waveforms - if you set the SSI to clock at 4MHz, then transmitting a byte will take 2 microseconds, so the time interval between the two bytes should be also 2 microseconds, or it shows around 4 - seems to be extra time spent without any reason (could be normal also, but should be an obvious reason - a benchmark would be useful here…)

 

On the waveforms - it would be useful to change the labels MOSI/MISO to something more clear - what you show is from what perspective? micro or your MFRC522 - should be labeled clearly as SSITX and SSIRX.

 

One more: to read something from a register you need to write something first. Did you tried that?

 

If still not working, you may try also to configure SSIFSS pin as normal GPIO output pin and manage it manually (many recommends this, sometimes SSI seems not working - I did not had such thing but..). 

L

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Hi,

Again about your expression of register 0 address: why do you shift left? It is not needed, just need to be masked with 0x7E and then set/clear bit 7.

L

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Hi,

Again about your expression of register 0 address: why do you shift left? It is not needed, just need to be masked with 0x7E and then set/clear bit 7.

L

// Address format:1XXXXXX0

it's a reason why we shift left, set last bit to 0, set first bit 1.

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Hi,

Please think again and review Table 8 in chip's data sheet. Only masking (AND ) with 0x7E clears bit 0 and 7, leaving bits 6..1 unaltered. Shifting to the left moves bit 6 in position 7 and in fact all content is altered.

Also, did you set the hardware correctly? I mean pin I2C=0 and pin EA=1 to automatically configure for SPI interface?

Modes 0 and 3 are the ones accepted.

L

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Hi,

Please think again and review Table 8 in chip's data sheet. Only masking (AND ) with 0x7E clears bit 0 and 7, leaving bits 6..1 unaltered. Shifting to the left moves bit 6 in position 7 and in fact all content is altered.

0x7e = 0111 1110

For example for read register 0x14 value i need to send

0x14 = 0001 0100

shift left << 1

0010 1000

mask (AND) with 

0111 1110

result is

0010 1000

and last - set first bit to 1
OR with 0x80
1000 0000
we have
1010 1000 <=> mask 1XXXXXX0
it's 0xA8
 
Something wrong?

 

Also, did you set the hardware correctly? I mean pin I2C=0 and pin EA=1 to automatically configure for SPI interface?

Modes 0 and 3 are the ones accepted.

oops.... i'm first time read this :(

Where is possible read more detailed info about this ?

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Hi,

The result of the operation should be 0x94 if want to read the register 0x14. Your example is by default in advantage. What about an address 0x64?

Shifting alters the content...

Also, the configuration mentionned is in Table 5, page 9.

L

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post-3079-14264605407046_thumb.jpg

We have only 6 bits and maximum possible is 0x3F.

 

SPI module working fine - i connect it to arduino and all working fine.

It's inside stellaris problem.

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