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Rei Vilo

[SOLVED] LaunchPad Stellaris on Energia - MISO Erratic Behaviour on SPI0 and SPI3

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SOLVED — see http://forum.stellarisiti.com/topic/675-solved launchpad-stellaris-on-energia-miso-erratic-behaviour-on-spi0-and-spi3/?p=3462

 

This thread continues a question I raised in [Energia Library] Stellaris Launchpad FatFs Energia library.

 

I'm experiencing an issue with MISO from SPI port 0: no signal coming to the MCU.

 

 

Hi Grant,

Try to add a pull-up resitor of 1K to MISO pin. The original driver enables the weak pull-up for MISO, but in the the Energia SPI lib it is not enabled. You can also try to set the MISO pin with pinMode(MISO, INPUT_PULLUP) before SPI.begin.

 

Regards,

Calin

 

 

I tried both of the suggested solutions, alas with no result.

 

The logic analyser shows a flat HIGH signal. Same for SPI3.

 

 

Summary:

 

  • SPI=SPI2 and SPI1 work fine
  • Issues with SPI0 and SPI3: MISO not ok, even with pull-up resistor or with digitalMode(pinMISO, INPUT_PULLUP) as suggested

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Digging into TI documentation, the Stellaris® LM4F120H5QR Rev A1/A3/B0 Errata reads on top of page 27:

 

 

 

GPIO
9.1 Some GPIO register bits default to the incorrect state Description:
The AFSEL bits for the following pins are set at reset, resulting in the pins defaulting to their alternate function:
This error in pin functionality may create pin conflict during any type of reset with the following signals:
 
Signal PA4
Function SSI0Rx
I/O Input
Level Tristate

 

and proposes as workaround

 

 

Workaround:

To reconfigure the pins to their intended reset state (GPIO Input, GPIODEN =0), software must clear the corresponding bits in the GPIOAFSEL and GPIODEN registers for the associated pins. For pins PD7 and PF0, software must clear the corresponding AFSEL bits using the register commit control procedures described in the Commit Control section in the General-Purpose Input/Outputs chapter in the data sheet.

Note that PD7 and PF0 should be grounded, if possible, to prevent triggering an NMI. If that is not possible, an NMI handler must be implemented in case a High level is applied to PD7 or PF0 before they can be reconfigured.

For PD7, the PMC7 assignment of 0x3 is not valid, so it does not cause any issues. However, for PF0, the PMC0 assignment of 0x3 specifies CAN0Rx. If the system design requires CAN0Rx to be on another pin, the PMC0 field for Port F must be assigned to another function or cleared.

Silicon Revision Affected:

A1

Fixed:

Fixed on A3. 

 

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Hi Rei,

Did you checked miso, mosi, sclk, ss signals during a byte transmissio on all SPI modules ? Maybe the SPI mode or the SS pin are not configured correctly and the slave does not recognize what is sent to it.

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Many thanks to @@reaper7 who helped me and fixed the problem!

 

Actually, it was a problem with the initialisation of the SPI ports.

 

Please find for the StellarPad.

Here is a comparison of the times, all in us —1 s = 10^9 us— measured with a Saleae Logic16 analyser at 100 MHz, ±0,01 us. Comma as decimal separator.

 

digitalWrite(HIGH) digitalWrite(LOW) = 0,73 us per cycle

setHIGH() - setLOW() = 0,26 us per cycle
pulseHIGH() = 0,19 us per pulse
pulseLOW() = 0,19 us per pulse
pulseLOW() x2 = 0,19 us per pulse and 0,26 us between pulses

 

 

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Hi!  I'm going to try this out, I need two fully functional SPI ports, but I have a Tiva-C board,  TM4C123G exactly.  Will all this stuff work with it?

 

Thank  you!

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