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Stupid question about UART FIFOs


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I'm coding a module for using the UART in the Stellaris Launchpad. I want to use FIFOs. My problem is with the documentation. LM4F120H5QR datasheet states each UART has a 16x8 FIFO for Tx and another 16x8 FIFO for RX. But I can't find what is the FIFO width and what is the FIFO depth.

 

Is the FIFO "16 bit x 8 elements", or is it "8 bit x 16 elements"?

 

PS: Why UART FIFO isn't documented like for example the SSI FIFO. For the SSI FIFO, the datasheet makes it clear: "Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep"

 
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I'm coding a module for using the UART in the Stellaris Launchpad. I want to use FIFOs. My problem is with the documentation. LM4F120H5QR datasheet states each UART has a 16x8 FIFO for Tx and another 16x8 FIFO for RX. But I can't find what is the FIFO width and what is the FIFO depth.

 

Is the FIFO "16 bit x 8 elements", or is it "8 bit x 16 elements"?

 

PS: Why UART FIFO isn't documented like for example the SSI FIFO. For the SSI FIFO, the datasheet makes it clear: "Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep"

 

 

I would say 8 bit wide and 16 deep as UART can only do 5, 6, 7, or 8 data bits

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I also thought about that, but when you read from the Rx FIFO, you get 12 bits (8 bits + 4 error bits). I don't know if the extra 4 bits are attached to the readed data and stored in the FIFO, or just added to the 8 data bits when doing the read operation.

Not sure. Might want to ask TI e2e.

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