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How to calc the clock


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Hello everyone. I have a problem to calc clock in code. @@.

When i code

//

SysCtlClockSet(SYSCTL_SYSDIV_2|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);

//

I can't calc clock.  Can you explain me to calc it.

Thank so much.

Since you are using the PLL which is at 400Mhz and then that is divided by 2. It is further divided by the divisor you specified which is 2.5

400Mhz/2/2.5 = 80Mhz

 

You can also get the current clock by issuing the following code after the above:

unsigned long
SysCtlClockGet(void)
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Sr about the question very easy. @@. If i use OSC

//

SysCtlClockSet(SYSCTL_SYSDIV_2|SYSCTL_USE_OSC|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);

//

How about that. Can you explain me.

And can you give me example when i use code:

//unsigned long SysCtlClockGet(void)

//

 

 

Thank you very much and if my question so noob. sr about it.

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Hello everyone. I have a problem to calc clock in code. @@.

When i code

//

SysCtlClockSet(SYSCTL_SYSDIV_2|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);

//

I can't calc clock.  Can you explain me to calc it.

Thank so much.

 

 

 

Since you are using the PLL which is at 400Mhz and then that is divided by 2. It is further divided by the divisor you specified which is 2.5

400Mhz/2/2.5 = 80Mhz

 

 

 

I am confused - what specifies the 2.5 divisor? 

The code sample looks like it specifies a divisor of 2.  Wouldn't you need to use (SYSCTL_SYSDIV_2_5 to get PLL/2.5 )

 

For instance project0.c uses SYSCTL_SYSDIV_4 and comments say the resulting clock is 50 MHz (200 MHz / 4 = 50 MHz)

So I would have thought that the code given here would specify a 100 MHz clock?

(Of course not all parts can reach a 100 MHz clock).

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  • 8 months later...

reading this (studying the clock stuff now)... yeah that code looks like it specifies a 100MHz clock.  Looks like to get 80MHz you have to use SYSCTL_SYSDIV_2_5 ... which enables the DIV400 bit (looks like all the SYSCTL_SYSDIV_x_5 defines use DIV400 mode so the initial /2 is ignored, and e.g. SYSCTL_SYSDIV_2_5 enables DIV400 with a divider of 5).

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  • 6 months later...

An anomaly with this: if you're using driverlib TivaWare_C_Series-2.1.0.12573 on a TM4C123GH6PM (i.e. an EK-TM4C123GXL launchpad) you can use

  SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ); /* 2*PLL/5 = 80 MHz */
to set the clocks to 80MHz, but if you then call SysCtlClockGet() it'll tell you you're running at 66MHz. This is because SYSCTL->DC1.MINSYSDIV, which driverlib consults, insists that the minimum divider is 3, so you can't possibly be running faster than 66MHz.

 

At least TI gives us the source code so we can figure these things out, and per this e2e post with a patch it'll be fixed some day.

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