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Fred

A new MSP430 coming [MSP432 ARM]

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Nice! Now let's see the linker script :D

Is this what you're after?

MEMORY
{
    MAIN       (RX) : origin = 0x00000000, length = 0x00040000
    INFO       (RX) : origin = 0x00200000, length = 0x00004000
    SRAM_CODE  (RWX): origin = 0x01000000, length = 0x00010000
    SRAM_DATA  (RW) : origin = 0x20000000, length = 0x00010000
}
Other interesting stuff I dug out from msp430p401r.h (That seems to be the only device in the family at the moment by the wy.)

 

There's a CMSIS style blinky example. It mentions CMSIS definitions a lot. Not sure if that's enough to keep @@pabigot happy.

 

From the header it would imply Cortex M4, not M0.

//*****************************************************************************

// CMSIS-compatible configuration of the Cortex-M4 Processor and Core Peripherals

//*****************************************************************************

#define __MPU_PRESENT 1 // MPU present or not

#define __NVIC_PRIO_BITS 3 // Number of Bits used for Prio Levels

#define __FPU_PRESENT 1 // FPU present or not

 

#endif // __CMSIS_CONFIG__

 

// Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File

#ifdef __TMS470__

#pragma diag_push

#pragma CHECK_ULP("none")

#include "core_cm4.h"

#pragma diag_pop

#else

#include "core_cm4.h"

#endif

Memory and peripherals, including ADC14, AES, CapTouch, DMA, DWT (Digital Watchpoint and Trace), EUSCI, Floating Point unit, ITM(?), Port Mapping (for 8 of the 10? 16-bit ports), Real Time Clock. [Probably stuff I've missed or misinterpreted.]

//*****************************************************************************

// Device memory map

//*****************************************************************************

#define __MAIN_MEMORY_START__ (0x00000000) /* Main Flash memory start address */

#define __MAIN_MEMORY_END__ (0x0003FFFF) /* Main Flash memory end address */

#define __BSL_MEMORY_START__ (0x00202000) /* BSL memory start address */

#define __BSL_MEMORY_END__ (0x00203FFF) /* BSL memory end address */

#define __SRAM_START__ (0x20000000) /* SRAM memory start address */

#define __SRAM_END__ (0x2000FFFF) /* SRAM memory end address */

 

//*****************************************************************************

// Peripheral memory map

//*****************************************************************************

#define __MCU_HAS_ADC14__ /* Module is available */

#define __MCU_HAS_AES256__ /* Module is available */

#define __MCU_HAS_CAPTIO0__ /* Module is available */

#define __MCU_HAS_CAPTIO1__ /* Module is available */

#define __MCU_HAS_COMP_E0__ /* Module is available */

#define __MCU_HAS_COMP_E1__ /* Module is available */

#define __MCU_HAS_CRC32__ /* Module is available */

#define __MCU_HAS_CS__ /* Module is available */

#define __MCU_HAS_DIO__ /* Module is available */

#define __MCU_HAS_DMA__ /* Module is available */

#define __MCU_HAS_EUSCI_A0__ /* Module is available */

#define __MCU_HAS_EUSCI_A1__ /* Module is available */

#define __MCU_HAS_EUSCI_A2__ /* Module is available */

#define __MCU_HAS_EUSCI_A3__ /* Module is available */

#define __MCU_HAS_EUSCI_B0__ /* Module is available */

#define __MCU_HAS_EUSCI_B1__ /* Module is available */

#define __MCU_HAS_EUSCI_B2__ /* Module is available */

#define __MCU_HAS_EUSCI_B3__ /* Module is available */

#define __MCU_HAS_FLCTL__ /* Module is available */

#define __MCU_HAS_FPB__ /* Module is available */

#define __MCU_HAS_PCM__ /* Module is available */

#define __MCU_HAS_PMAP__ /* Module is available */

#define __MCU_HAS_PSS__ /* Module is available */

#define __MCU_HAS_REF_A__ /* Module is available */

#define __MCU_HAS_RSTCTL__ /* Module is available */

#define __MCU_HAS_RTC_C__ /* Module is available */

#define __MCU_HAS_SYSCTL__ /* Module is available */

#define __MCU_HAS_TIMER32__ /* Module is available */

#define __MCU_HAS_TIMER_A0__ /* Module is available */

#define __MCU_HAS_TIMER_A1__ /* Module is available */

#define __MCU_HAS_TIMER_A2__ /* Module is available */

#define __MCU_HAS_TIMER_A3__ /* Module is available */

#define __MCU_HAS_TLV__ /* Module is available */

#define __MCU_HAS_WDT_A__ /* Module is available */

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M4F at that if the FPU really is there! So TI took a Tiva, gave it some msp430-like peripherals (presumably for lower power? Or maybe just for familiarity with its target audience?) and also presumably made it close to being in the same category as the msp430 power consumption-wise? (Or at least we assume....) That's pretty juicy stuff!

 

Sent from my Galaxy Note II with Tapatalk 4

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Also that's 256KB flash, 16KB Infomem flash and 64KB SRAM. Not sure what the SRAM code vs data stuff is. Maybe a Harvard architecture quirk? I think ARM usually is a "modified harvard architecture"

 

Sent from my Galaxy Note II with Tapatalk 4

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I noticed that the part number in the CCS screenshot is MSP432P401R, so I guess we know that the "4" in "P401R" means Cortex M4.  Frankly I wouldn't mind a regular-old M3.  M0 and M0+ use a different version of ARM, and there are actually some porting issues between M3/M4 -> M0 ... so I don't mind if M0/M0+ is not in the product family.  On the other hand, if I can save some power and cost by choosing M3 instead of M4F, I will usually make that choice.  Hardware floating point is not so important for my work.

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I'm sure there will be more coming in the family. The overlap with Tiva seems a bit odd though. The theories about M0 made more sense. I wonder if more will migrate over and TI will make a break from the Luminary Micro past? Time will tell.

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I'm sure there will be more coming in the family. The overlap with Tiva seems a bit odd though. The theories about M0 made more sense. I wonder if more will migrate over and TI will make a break from the Luminary Micro past? Time will tell.

My guess is Tiva will continue, but most likely make a break for Cortex-M7 at some point. I bet such developments are already well under way but will take years to come to fruition. After all, someone said msp432.com was registered back in 2011...

 

Sent from my Galaxy Note II with Tapatalk 4

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I just notice that the CCS6.1 installation added the following link. It's for the MSP-TS432PZ100 target board. There's a full schematic, etc. but it doesn't give much more away about the MSP432 to be honest.

http://www.ti.com/lit/ug/slau571/slau571.pdf

 

There's also a broken link to CCS for MSP432 User's Guide (slau575).

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I just notice that the CCS6.1 installation added the following link. It's for the MSP-TS432PZ100 target board. There's a full schematic, etc. but it doesn't give much more away about the MSP432 to be honest.

http://www.ti.com/lit/ug/slau571/slau571.pdf

 

Nice find. A few observations:

  • GPIO follows MSP430 naming convention (P1.0 vs. Tiva PA0)
  • Peripherals names identical with MSP430F5xxx family (TA0..3, UCA0..3, UCB0..3)
  • 24 analog inputs A0..23
  • 8 SPI, 4 I2C, 4 UART
  • BSL/SBW connector with same pinout as MSP430 target boards (not sure if that was also the case for Tiva) not identical, so probably not programmable with old launchpads
  • No USB :(

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I just notice that the CCS6.1 installation added the following link. It's for the MSP-TS432PZ100 target board. There's a full schematic, etc. but it doesn't give much more away about the MSP432 to be honest.

http://www.ti.com/lit/ug/slau571/slau571.pdf

 

There's also a broken link to CCS for MSP432 User's Guide (slau575).

 

Just curious, how'd you find that...

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@@zlalanne We?? So you're on the inside, eh? ;-) I must admit I didn't notice your location.

 

Sorry if I leaked something I shouldn't, but you know we're all hungry for info here! Anything you can share with us would be appreciated. Or if you need any beta testers...

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@@Fred no worries, good sleuthing on your point. I contributed to that document so I was just surprised/impressed it was found already

 

and yes full disclosure I work at TI within MSP430. Mostly work on MSPWare, DriverLib and a lot of our internal tools/infrastructure. Also did a lot of work on the MSP432 tools so I'm excited for it to be out in the open soon

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