abecedarian 330 Posted August 6, 2014 Share Posted August 6, 2014 http://www.parallax.com/microcontrollers/propeller-1-open-source Parallax Propeller 1 P8X32A Released as Open Source DesignThe Propeller 1 (P8X32A) is now a 100% open multicore microcontroller, including all of the hardware and tools: Verilog code, Spin interpreter, PropellerIDE and SimpleIDE programming tools, and compilers. The Propeller 1 may be the most open chip in its class.We have decided to provide these free open source files for the following reasons: tripwire, greeeg, roadrunner84 and 1 other 4 Quote Link to post Share on other sites
bluehash 1,581 Posted August 7, 2014 Share Posted August 7, 2014 Wow..In a way that is good news... but was it due to sales? Quote Link to post Share on other sites
abecedarian 330 Posted August 7, 2014 Author Share Posted August 7, 2014 @@bluehash Not really sure the motivation. But I think this raises the bar for everyone else in the MCU marketplace. I mean everyone: Atmel, ST, TI even, might just have to bring something like this to the table. And with the core 'open', who knows where it will go. bluehash 1 Quote Link to post Share on other sites
oPossum 1,083 Posted August 7, 2014 Share Posted August 7, 2014 No, not due to sales. Sales are fine at Parallax. They have been releasing a FPGA bitstream for the Propeller 2 that has been under development. The community really like being able to test a next gen chip before it became available. The release of a VHDL and bitstream for a Propeller 1 workalike will in no way harm sales of the Propeller chip. The FPGA is much more expensive then a propeller chip, and it would not be cost effective for a competitor to have an ASIC made. It is simply something they are doing for a few in the community that can hack away at the VHDL and do cool stuff. bluehash, OppaErich and tripwire 3 Quote Link to post Share on other sites
SixSixSevenSeven 23 Posted August 7, 2014 Share Posted August 7, 2014 I do have 2 propeller boards. On paper its very interesting to have 8 cores running simultaneously, but the reality is that you don't get to use those 8 cores fully. Each core has 2 counter modules which are simply somewhat basic timers (no interrupts or output abilities from them) and that is it for peripherals on the entire chip. PWM, Servos, communications all need bitbanging and that will usually use up a few of your cores in a project. Its still useful, but it would have been a better product with some actual on chip peripherals. One of my boards I will be fitting with VGA, RCA and PS/2 connectors and using it as a slave device for graphics and input, thats a genuine project I think it is well suited to (they can drive VGA signals quite nicely as well as PAL and NTSC) but I'm honestly not too sure what to do with the other, maybe a hexapod? bluehash 1 Quote Link to post Share on other sites
abecedarian 330 Posted August 14, 2014 Author Share Posted August 14, 2014 It's true that on the surface, the IP core is the chip, but with the source code for the core, you can make the chip what you want, within the constraints of your FPGA of course. Want native ADC- add it. Want interrupts, add them. People are already doing things and Parallax has voiced the possibility of producing chips with 'community' added functionality like ADC, DAC and other things. I just reported the information. Quote Link to post Share on other sites
Druzyek 36 Posted August 14, 2014 Share Posted August 14, 2014 On paper its very interesting to have 8 cores running simultaneously, but the reality is that you don't get to use those 8 cores fully I think most people misunderstand the philosophy behind the propeller. They left out all of the timers and interrupts on purpose and you have 8 cores so you can do the same as you could with 1 core and loads of peripherals. The difference is you now have room for 7 custom peripherals and 1 main core. I'm not sure why you would want 8 cores running simultaneously anyway. Efficiently using even 2 cores for 1 task is a non-trivial problem. Other microcontrollers handle multiple tasks with 1 core. Why not give each task its own core and eliminate other problems like interrupt latency while you're at it? oPossum 1 Quote Link to post Share on other sites
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