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Clock Settings issue with ACLK XT2


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I'm trying to run my ACLK from XT2 and the MCLK, SMCLK from DCO. According to the datasheet I should be able to do this. I'm using a MSP430F5529LP. If I remove the stabalization loop from the code I get 7.8 MHz from all the clocks. I can never get the ACLK to work with XT2 even if I remove all traces of DCO, MCLK, SMCLK. What am I missing to enable XT2????????  

 

void main(void)
{
Port_Mapping(); // Access port mapping code for MCLK output Pin
 
SetVcoreUp (0x01); // Increase Vcore setting to level 3 to support 25MHz.
SetVcoreUp (0x02);
SetVcoreUp (0x03);
 
WDTCTL = WDTPW + WDTHOLD;       // Stop watchdog timer
 
/////// Clock Settings //////////
// Loop until XT1,XT2 & DCO stabilizes
 do
 {
   UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);        // Clear XT2,XT1,DCO fault flags
   SFRIFG1 &= ~OFIFG;                      // Clear fault flags
 }
 while (SFRIFG1&OFIFG);                   // Test oscillator fault flag
 
UCSCTL1 |= DCORSEL_4;             // DCORSEL =4 (12.3 to 28.2 MHz range)
UCSCTL4 |= SELM__DCOCLK + SELS__DCOCLK + SELA__XT2CLK;         //Selects MCLK, ACLK, SMCLK
 
UCSCTL6 &= ~XT2OFF;
UCSCTL6 |= XT2DRIVE_2;        // XT2DRIVE 0 is 4 MHz, 1 is 12 MHz, 2 is 20 MHz, 3 is 32 MHz
UCSCTL2 = 762;    // Should give 25 MHz from DCO
 
UCSCTL8 = SMCLKREQEN + ACLKREQEN;
 
/////// Output Pins /////////
P2SEL |= BIT2;     // SMCLK Output Pin
P2DIR |= BIT2;
P1DIR |= BIT0;    // Output for ACLK
P1SEL |= BIT0;
P5SEL |= BIT2 + BIT3; // Port select XT2
 
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Moving the P5SEL before the loop solved the problem. Thanks for that tip.

My issue now is that the XT2 frequency doesn't change when I change XT2DRIVE_x. It always stays at 4 MHz. Am I misunderstanding that the freq can be altered above 4 MHz??? In the datasheet it shows XT2DRIVE_1 = 12 MHz  XT2DRIVE_2 = 20 MHz.

 

One strange think is the MCLK and SMCLK will only work if they're set to XT1 and not DCO. It works and I can alter the freq up to 25 MHz so I'm not going to complain but can anyone explain this?

UCSCTL4 |= SELM__XT1CLK + SELS__XT1CLK;  WORKS

UCSCTL4 |= SELM__DCOCLK + SELS__DCOCLK; DOESN'T WORK

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My issue now is that the XT2 frequency doesn't change when I change XT2DRIVE_x. It always stays at 4 MHz. Am I misunderstanding that the freq can be altered above 4 MHz??? In the datasheet it shows XT2DRIVE_1 = 12 MHz  XT2DRIVE_2 = 20 MHz.

Yes, you're misunderstanding that. The crystal is a physical device with a fixed frequency, and the EXP430F5529LP has a 4MHz one installed. The higher drive settings are used when a higher frequency crystal is installed.

 

One strange think is the MCLK and SMCLK will only work if they're set to XT1 and not DCO. It works and I can alter the freq up to 25 MHz so I'm not going to complain but can anyone explain this?

UCSCTL4 |= SELM__XT1CLK + SELS__XT1CLK;  WORKS

UCSCTL4 |= SELM__DCOCLK + SELS__DCOCLK; DOESN'T WORK

I don't really understand how you can get a 25MHz MCLK out of the 32 kiHz XT1, but if it works for you then what you're doing is probably not what you think you're doing. Here's one reason:

 

The power-up configurations for SELS and SELM are 100b, for DCOCLKDIV. The bits for XT1 are 000b, and for DCOCLK they're 011b. When you use bitwise or to reconfigure the register the first statement has no effect, and the second produces is a reserved value 111b that's supposed to be equivalent to selecting XT2CLK.

 

You probably don't want to be using |=, but instead something more like:

  UCSCTL4 = (UCSCTL4 & ~(SELS_7 | SELM_7)) | (SELS__DCOCLK | SELM__DCOCLK);
which is intended to mask the SELS and SELM fields to all zeros except for the bits required for DCOCLK.
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