How to safely connect a pot to the ADC

[DanAndDusty 62]

Hi all,

 

Im a software guy starting to get to grips with the MSP430 (and the electronics world as a whole). I grok the digital domain fairly well but at the moment its the analog side Im getting to know.

 

Im about to try and get to know the ADC side of the MSP430 and as a test I want to put a pot onto it and display the readings on a nokia 3310 LCD display. I have the display working well and I know how I plan to attack the ADC side, but my question is regarding the safest way of connecting the pot to the MSP.

 

My understanding is connect the outer pins of the POT to VCC and GND with the center pin (slider) to the ADC pin on the MSP. I have a 22K Linear rotary pot lined up. From what I can work out the pot acts as a voltage divider and that all makes sense. My query is how to handle the case when the pot is fully rotated. When the GND side is almost 0 ohms the VCC side will be about 22k and all will be well.. however in the converse situation the VCC side is about 0 ohms all the juice has a free smooth path to the ADC pin and there will be nothing to restrict the current.

 

My options (as I see them) are:

 

1) A 10k resister between VCC and the top pin of the pot. The top side will then range between 10k and 32k ohms, with the bottom side going between 0 and 22k. My guess is that the full range of voltages will not be presented to the ADC pin.

 

2) A 10k resistor between the centre pin (slider) and the ADC pin. Top and bottom with both then range between 0 and 22k but the current path will always have atleast the 10k resistor to limit the current. I don't know if 10k+22K would restrict the current too much though.

 

3) Do nothing. The MSP will limit the current or not be damaged by it. I have googled this question and most sites I have seen seem to have have no limiting resisters but don't say whether this issue was considered.

 

So I hope this question is clear enough and you guys/gals can further my quest for knowledge. If I was just going for it I think I would go for option 2 as my gut feeling is it supplies enough protection without restricting the ranges.

 

Many thanks in advance

 

Dan

[RobG 1,892]

Option #3. ADC input has internal resistance of ~2k, draws very little current, and has built in over voltage protection.

[DanAndDusty 62]

Option #3. ADC input has internal resistance of ~2k, draws very little current, and has built in over voltage protection.

 

Thanks for the information. Reading the sheet I couldn't find anything about the internal resistance and didn't fancy blowing my board up.

 

As I said in my first post Im new to all this electronics millarky and so I don't quite understand the "draws very little current". I thought that unless there was something there to limit the current then all the current available could flow. Do you happen to know any good resources on reading up more on all this?

 

Thanks again for the prompt answer though.. my experiments can continue in (relative) safety.

[RobG 1,892]

...Reading the sheet I couldn't find anything about the internal resistance...

See the family user guide.

 

... I don't quite understand the "draws very little current". I thought that unless there was something there to limit the current then all the current available could flow...

Simplifying things, during sampling, a switch for the selected channel is closed and charges tiny capacitor (~27pF) and that is the only current flowing through this circuit, we are talking uA here over the period of few us. Once the cap is charged, there is no more current flowing. Then that switch is opened and another closed, one that connects the capacitor to a comparator. Comparator then compares capacitor's voltage to a reference voltage which is connected through resistor network (basically a DAC.)

When the whole converting cycle is done, SAR's value is written to memory register.

 

How SAR works?

For example you have 15V voltage reference and a 4 bit SAR with a ladder of resistors that can output 0-15V, bit0 1V, bit1 2V, bit2 4V, and bit3 8V. It's output is connected to a comparator. S&H capacitor is also connected to a comparator and is charged during sampling cycle to 7V.

Converting cycle begins and bit3 is turned on, comparing 8V to 7V, because it's bigger, bit3 stays off, next bit2 is on and 4V is compared to 7V, since 4V is smaller than 7V bit2 stays on, then bit1 is set, comparing 6V to 7V (6V because bit2 is still on 4V + 2V.) 6 is less than 7, bit1 is on. Next bit0, 7V is not more than 7V, bit0 is on. End of converting cycle, SAR register is 0111 and it's written to mem register.

 

How many cycles this whole process takes?

You must have enough cycles to charge the capacitor (sampling time,) the bigger output resistance of the measured circuit, the longer it will take to charge it. This usually takes few us, but sometimes when you have dividers with mega ohm resistors, it may take several tens of us.

The comes converting, one cycle for each bit of resolution so 10bit ADC will require 10 cycles.

Figuring out sampling time is important because it will introduce error if it is too short and the capacitor is not charged to the input voltage.

[DanAndDusty 62]

Wow.. thanks for the very informative reply. You have definitely increased my understanding. I don't have a head for facts+figures. I can't remember things that way. What I need is an understanding, an internal model so to speak. New knowledge has to hang off that model and I can "see" how things are doing what they do. Your explanation makes sense to me and I can totally see why an additional resistor connected to the pot is un-necessary.

 

I knew there was a time needed for the ADC process, but didn't quite know why, now I do.

 

So thanks again, your time taken to answer my questions is much appreciated