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pabigot

EXP430FR5969 clock speed above 8MHz

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On my Wolverine LP, attempts to set the clock speed to 16MHz result in an oscillator fault as soon as CSCTL3.DIVM is cleared to remove the power-up divider.  This is not listed as an erratum for the MCU.  Has anybody confirmed a working board running with MCLK at 16MHz?  The datasheet says it should work up to that speed; it may just be that my specific device is unreliable.

 

The board does run at 12MHz with DCOCLK at 24MHz and DIVM_2.

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It might be your unit. I tested mine and it is running at 16Mhz

FRCTL0 = 0xA500 | ((1) << 4);  //FRCTLPW | NWAITS_1;
	
CSCTL0 = CSKEY; // unlock CS module registers
CSCTL1 = DCORSEL | DCOFSEL_4; // Set DCO to 16Mhz

CSCTL3 &= ~(0x0007); // clear all the DIVM bits

// expose MCLK on IO pin.
PJSEL0 |= BIT1;
PJSEL1 &= ~BIT1;
PJDIR |= BIT1;


This is the code I thew together. Using the advisement from the rev D -> E migrating guide (slaa611) to define FRAM wait states.

 

The FRAM wait state register isn't defined in my header files so it's been explicitly written. I can confirm 16Mhz output on PJ.1

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It might be your unit. I tested mine and it is running at 16Mhz

FRCTL0 = 0xA500 | ((1) << 4);  //FRCTLPW | NWAITS_1;

Nope, it was my missing the need to set wait states. Once I do that, I can actually run the thing at 24MHz (though it's only rated to 16MHz). I've updated bsp430 to support it with this patch.

 

Some interesting points:

  • The FR57xx devices support auto configuration of wait states; this was what was described in the FR58xx user's guide at slau367, but slau367a updates it
  • The gloss in the device data sheets specify that wait states are determined by MCLK frequency, but I don't think that's right: you can divide MCLK to be 8MHz, and still have SMCLK at 16MHZ, and I believe the wait states would have to be increased so that DMA would work.

The FRAM wait state register isn't defined in my header files so it's been explicitly written.

Back in the day, the password was FWPW and the wait states would be set to one by FRCTL0 = FWPW|(1*NACCESS0). Newer headers use NWAITS0 instead of NACCESS0, and add FRCTLPW.

 

This is the sort of confusion you get when you're an unofficial beta tester, I guess.

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In the F59xx userguide the revision history seems to indicate that the wait states used to be automatic.

Section 5.5 Removed the option for automatic wait state control.

This is probably as you say, to let users run the DMA using a SMCLK > MCLK.

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