Why are the SR bits cleared on exit?

[nissa 0]

I'm following the attached I2C example code provided by TI. The MCU is put into LPM0 with three interrupts enabled.

On a pending RX interrupt, the ISR stores one byte of the receive buffer and clears the LPM0 SR bits taking the MCU out of LPM0 (lines 133-135). What's the reason for exiting LPM0? And why isn't the __bic_SR_register_on_exit(LPM0_bits) used for the NACIFG and BCNTIFG?

msp430fr235x_euscib0_i2c_10.c

[StefanSch 10]

The golden rule is that an Interrupt Service Routine (ISR) should be as short as possible. Therefore the received data is just stored and then evaluated outside of the ISR. This examples is really very minimalistic - is should better store the data in a buffer instead of a single bit and trigger the evaluation once a full frame has been received. This evaluation than should of course being outside of an ISR. Having this task outside of the ISR ensures proper execution of the code and esp. handling interrupts right in time. Note: during interrupt execution other interrupts are blocked.

So the LPM is cleared the enable execution in the main function again, otherwise the CPU would go into sleep mode again after the ISR.

The __bic_SR_register_on_exit cannot clear any of the interrupt flags.

The I2C interrupt flags are automatically cleared by switch(__even_in_range(UCB0IV, USCI_I2C_UCBIT9IFG)) - more details are in the Users Guide