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New (soon to be) valueline chip. MSP430G2955 56kb Flash 4kb Ram!


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Just noticed this on the TI valueline list. http://www.ti.com/product/msp430g2955 Not many details, even though it's marked Active and not preview. No Datasheet, no summary. Just the specs.   Key F

So they are releasing PDIP-40 versions then.  The TI news article mentions the MSP430 LaunchPad Expansion board, available in May -- https://www.olimex.com/Products/MSP430/Booster/MSP430-G2744BP/?DCMP

It was showing up in the parametric search. What's more, PS lists 44 parts, but the product tree has 45 parts.   BTW, remember this?

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So they are releasing PDIP-40 versions then.  The TI news article mentions the MSP430 LaunchPad Expansion board, available in May -- https://www.olimex.com/Products/MSP430/Booster/MSP430-G2744BP/?DCMP=mspvalue-g2xx&HQS=mspvalue-g2xx-olimex-pr-lp (guess they partnered with Olimex for that one).

 

It stuffs a PDIP-40 up top and breaks it out into 40-pin XL sized headers.

edit: G2744 at least.  The "PDIP available in sampling quantities" thing.  Guess that's a one-off run for their Olimex expansion board.

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Just got an email too: post-44-0-34397600-1364316001_thumb.png

 

The data sheet links are the same as on the g2744 and g2955 pages. Both of those are available for sampling now.

 

With the video being:

http://focus.ti.com/general/docs/video/Portal.tsp?entryid=0_sa3dsbvp&DCMP=mspvalue-g2xx&HQS=mspvalue-g2xx-em-v&sp_rid_pod4=OTE2NTUwNzY3MQS2&sp_mid_pod4=41219500

 

The video also mentions the DIP 40 Pin package.

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An obvious benefit of these, which I hadn't even thought of until on3pk's discussion about data-flash ("EEPROM") writing, is the practicality of reserving larger segments of this main program flash for data write-back.

 

How does writing to program flash generally work if done from program code in the flash?  Looking at the x2xx user's guide it seems like it's functional except during any flash erase or write operations the program can't really run, it just spins in place, but I guess writing a data-designated section of the program flash is doable.  With 4KB SRAM there's plenty of scratch to temporarily store the 512-byte segments of main program flash for when you need to "update" stored data already in place.

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There is no MSP430F2744. There's an MSP430F2274, which is identical to the MSP430G2744 in terms of memory and peripherals except it has on-board opamps. The internal architecture of the value-line series would change power profiles, chip errata, and possibly the accuracy of calibration constants.

llc[12]$ egrep 'Name|2..4' /msp430/msp430mcu/upstream/devices.csv 

# Device Name,CPU_TYPE,CPU_Bugs,MPY_TYPE,SBW,EEM,BREAKPOINTS,CLOCKCONTROL,CYCLECOUNTER,STACKSIZE,RAMStart,RAMEnd,RAMStart2,RAMEnd2,USBRAMStart,USBRAMEnd,MirrowedRAMSource,MirrowedRAMStart,MirrowRAMEnd,BSLStart,BSLSize,BSLEnd,INFOStart,INFOSize,INFOEnd,INFOA,INFOB,INFOC,INFOD,FStart,FEnd,FStart2,FEnd2,Signature_Start,Signature_Size,INTStart,INTEnd

msp430f2234,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,0200,03FF,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDD,0,0,,,FFE0,FFFF

msp430f2254,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,0200,03FF,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDD,0,0,,,FFE0,FFFF

msp430f2274,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,0200,05FF,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,8000,FFDD,0,0,,,FFE0,FFFF

msp430g2444,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,0200,03FF,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,E000,FFDD,0,0,,,FFE0,FFFF

msp430g2544,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,0200,03FF,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,C000,FFDD,0,0,,,FFE0,FFFF

msp430g2744,0,0,0,1,EMEX_LOW,2,STANDARD,0,80,0200,05FF,0,0,0,0,0,0,0,0,0,0,1000,40,10FF,10C0,1080,1040,1000,8000,FFDD,0,0,,,FFE0,FFFF

llc[13]$ diff -u /msp430/msp430mcu/analysis/peripherals/msp430{g274,f227}4.periph

--- /msp430/msp430mcu/analysis/peripherals/msp430g2744.periph 2013-03-25 13:32:48.522471649 -0500

+++ /msp430/msp430mcu/analysis/peripherals/msp430f2274.periph 2013-03-25 13:32:47.541478264 -0500

ADC10

BC2

FLASH2

+OA_2

PORT1_R

PORT2_R

PORT3_R

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