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M-atthias

Bit-Bang USB on MSP430G2452

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I would like to see an C implementation of this. Also if it is possible to modify the code for this to operate with 16 MHz crystal it would be great too, because I think 16M is more common frequency than 18M. 

 

Anyways, great job!

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This project is spectacularly important. I could really use an inexpensive USB interface in many MSP430 projects, where an FT232RL is simply out of the question because of the price! Most of the time I only really need a simple UART.

 

Congratulations on your first successes, and I'm hoping to see more soon.

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I reached the next milestone !

Mecrimus-B 0.3 is out and freshly supports clocking with 15 MHz.

Because bit clock is 1.5 MHz, frequencies for Mecrimus-B have to be an integer multiply of that. 16 MHz would be REALLY tricky.

Do you already have testing results for me ?

Matthias
 

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One question here has been very interesting:

 

Would it possible to run Mecrimus-B with a common 32768 Hz crystal in place ?

 

 

For that, I measured the DCO frequency steps with Timer-A capture relative to 32768 Hz ACLK in a spare MSP430G2553 with RSEL=15:

 

DCOCTL  kHz     Difference  (Frequency-15MHz)/15MHz

                to 15MHz

                in kHz

 

120     14352   -648    -0.0432

121     14397   -603    -0.0402

122     14438   -562    -0.0375

123     14454   -546    -0.0364

124     14483   -517    -0.0345

125     14528   -472    -0.0315

126     14581   -419    -0.0279

127     14614   -386    -0.0257

128     14639   -361    -0.0241

129     14675   -325    -0.0217

130     14700   -300    -0.0200

131     14741   -259    -0.0173

132     14774   -226    -0.0151

133     14819   -181    -0.0121

134     14843   -157    -0.0105

135     14868   -132    -0.0088

136     14901   -99     -0.0066

137     14933   -67     -0.0045

138     14983   -17     -0.0011

139     15020   20      0.0013

140     15048   48      0.0032

141     15089   89      0.0059

142     15101   101     0.0067

143     15134   134     0.0089

144     15183   183     0.0122

145     15232   232     0.0155

146     15273   273     0.0182

147     15294   294     0.0196

148     15339   339     0.0226

149     15396   396     0.0264

150     15417   417     0.0278

151     15470   470     0.0313

152     15511   511     0.0341

153     15568   568     0.0379

154     15589   589     0.0393

155     15654   654     0.0436

156     15691   691     0.0461

157     15724   724     0.0483

158     15790   790     0.0527

159     15814   814     0.0543

 

 

The longest packets to receive are 11 Bytes, and within 88 Bytes, there may be 15 stuffing bits, which gives a total of 103 Bits.

For keeping sync stable, there may be an error of roughly 1/3 of bittime.

 

This gives for the required accuracy:

103*Accuracy=1/3 --> 0.0032.

We have three steps in DCOCTL that match this requirement.

 

If DCOCTL frequency step sizes are roughly equal in different msp430 microcontrollers (absolute DCOCTL values are not the same and fluctuate with temperature and Vcc), then this opens up a possibility.

 

A quick test with SMCLK output on P1.4 and manual adjusting the DCOCTL register values in my msp430g2452 to get frequency right allowed Mecrimus-B 15 MHz to work as long as temperature and VCC were kept constant.

 

As you can configure Timer-A to capture SMCLK on egdes of ACLK, which I did to measure the DCO step frequencies, you can implement a frequency control loop which is called in regular intervals to keep track with slowly changing temperature and Vcc.

 

For 18 MHz, the step resolution of DCOCTL is more coarse, and I would prefer the finer tuning possibilities around 15 MHz.

 

Would you like to see this implemented ? If Mecrimus-B proves its stability with accurate crystal clock, then this idea could be the next step.

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Would you like a surprise ? A very special one indeed ?

Mecrimus-B 0.4 runs on a MSP430F2012 with a 32768 Hz crystal !


post-25024-0-17377800-1355190599_thumb.jpg


D+ with 50 Ohms on P1.0
D- with 50 Ohms on P1.1

Pullup with 1.5 kOhms for D- hardwired to Vcc
Sync-LED on P1.2 (Anode with 100 Ohms) and P1.3 (Cathode)
SMCLK for measurements on P1.4

32768 Hz crystal on XIN/XOUT

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sweet...

 

how much flash got left. u got to do a simple demo to show this off. something like blinking / cycling the keyboard leds, etc.

 

will definitely attract testers / developers.

 

/EDIT.. is the clock stable enough for prolong operation?

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For demonstration, it introduces itself as HID mouse and moves your pointer !

Long-time stability of 32768 Hz crystals should be excellent and inside Mecrimus-B current DCO frequency is captured relative to ACLK and adjusted in background to keep track with changing temperature.

All this occupies 1890 Bytes - you have ~150 Bytes free. I will try to shrink code size a bit more.

Matthias
 

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D+ with 50 Ohms on P1.0

D- with 50 Ohms on P1.1

 

Pullup with 1.5 kOhms for D- hardwired to Vcc

Sync-LED on P1.2 (Anode with 100 Ohms) and P1.3 (Cathode)

SMCLK for measurements on P1.4

 

32768 Hz crystal on XIN/XOUT

 

your photo does not match your description. the resistor count / color ring does not match up.

i could follow your description as they are similar to v-usb setup.

 

i would like to know how u supply Vcc to the f2012 and what is the electrolytic capacitor doing there, can u explain that?

 

thanks.

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- Two times two 100 Ohms resistors in parallel for 50 Ohms on data lines
- One 1kOhms and one 470 Ohms in series for needed ~1.5 kOhms pullup
- 15kOhms between Vcc and Reset
- High-Brightness red Sync-LED in clear case has 100 Ohms resistor

5V from USB is fed through two 1N4148 diodes connected to 100uF capacitor for smoothing. You can try smaller capacitors if you wish. Power status standard red LED with 220 Ohms resistor is next to it. This is required, as without any power consumption, Vcc may rise to about 4V. With power status LED, Vcc is 3.5V.

Yes, this is very similar to V-USB schematics.
 

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For demonstration, it introduces itself as HID mouse and moves your pointer !

 

Long-time stability of 32768 Hz crystals should be excellent and inside Mecrimus-B current DCO frequency is captured relative to ACLK and adjusted in background to keep track with changing temperature.

 

All this occupies 1890 Bytes - you have ~150 Bytes free. I will try to shrink code size a bit more.

 

Matthias

 

The code size isn't too bad, especially with the bigger valueline that come with the v1.5 launchpad. 8 to 16kb. Portability is better. Also, this is amazing.

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Something that might help, if would like to use it.  is the sync code i developed for my USB project (currently stalled in data handling but still moving :smile:  It is able to capture the sync signal and align to a single clock pulse to the sync signal and it catches every single one, rather than waiting for one to happen to align.  the theory is based on the fact that a MSP430 will take some random amount of clocks to enter an interrupt look due to the variable instruction length it has to finish.  functionally this can span 7 clock cycles in my testing (15 MHZ clock)  so i built a half-split based delay tree to realign the clock to the longest possible iteration so that my program can run accurate to the USB signal.  after it aligns to the sync is manually bit captures the last 4 bit states to see if it was a valid "sync" byte.  it is built to read D+, but could easily be rebuilt to work from d-.  It is hard to describe exactly how it flows but I will do my best if you are interested. It is hard to describe exactly how it flows but I will do my best if you are interested.  It is also fairly compact code size wise.  It uses the SPI interface to record an 8 bit sample at 1 sample per clock to get a hires picture of a bit transition, then picks out where the transition happened, and aligns to it.  The latest entering iteration drops straight through with minimal delays, and the earlier entering iterations are delays successively longer by 1 cycle until it can handle all 7 iterations

 

I would like to help however I can.  your initial email is actually what prompted me to teach myself assembly code to try and understand your code.

 

 

I am still having trouble reading your assembly directly because it is written for a slightly different complier than CCS, but I will help where I can.  the theory should be applicable to your code, albeit it would mean a hybrid of bit bang, and using SPI for the alignment.

 

Here is the code as it is for CCS assembly (which should be the raw MSP430 commands) the interrupt is called from d+ going high, like yours is

P1IntSync	nop					 ;1 cycle delay 
		mov.b	#0x00,		R14 		;1 Clear R14 for data check
		mov.b   #0xAA,		&UCA0TXBUF	;4  dummy TX write to allow RX capture
        	bic.b   #0x08,          &P1IE        	;4 disable D+ Interrupt ---//=================================//
		bic.b   #0x08,          &P1IFG        	;4 reset D+ Interruptflag  // Wait 8 cycles for SPI to record //
                            				;  ------------------------//=================================//
		mov.b	&UCA0RXBUF,	R15		;3 copy RX buffer to register
AlignStart	bit.b	#0x08,		R15		;1 Half Split Top or Bottom Half of Byte - Bits 7,6,5,4 / 3,2,1,0
		nop					;1 cycle delay
		jnc	BTMA				;2 Jump to Bottom Half Branch - Bits 7,6,5,4
		jmp	TOPJ1				;2 2 Cycle Delay for Top Half
TOPJ1		jmp	TOPJ2				;2 2 Cycle Delay for Top Half
TOPJ2		bit.b	#0x08,		&P1IN		;4 record data bit for synccheck (X... capture)
		rlc.b	R14				;1 feed data into synccheck
		bit.b	#0x02,		R15		;1 Half Split for Top Nibble - Bits 3,2 / 1,0
		jnc	TOPA				;2 Jump to Bits 2 & 3 branch
		jmp	TOPJ3				;2 2 Cycle Delay
TOPJ3		bit.b	#0x08,		&P1IN		;4 record data bit for synccheck (.X.. capture)
		rlc.b	R14				;1 feed data into synccheck
		bit.b	#0x01,		R15		;1 Half Split between Bits 0/1
		jnc	TOPC				;2 Jump around Bit 0 Delay
		nop					;1 1 Cycle Delay for Bit 0
TOPC		jmp	AlignDone			;2 Jump to AlignDone exit point
TOPA		bit.b	#0x08,		&P1IN		;4 record data bit for synccheck (.X.. capture)
		rlc.b	R14				;1 feed data into synccheck
		bit.b	#0x04,		R15		;1 Half Split between Bits 3/2
		jnc	TOPB				;2 Jump around delay for Bit 2
		nop					;1 1 Cycle delay for Bit 2
TOPB		jmp	AlignDone			;2 Jump to AlignDone exit point
BTMA		bit.b	#0x08,		&P1IN		;4 record data bit for synccheck (X... capture)
		rlc.b	R14				;1 feed data into synccheck
		bit.b	#0x20,		R15		;2
		jnc	BTMB				;2
		bit.b	#0x08,		&P1IN		;4 record data bit for synccheck (.X.. capture)
		rlc.b	R14				;1 feed data into synccheck
		bit.b	#0x10,		R15		;2
		jnc	BTMC				;2
		nop					;1
BTMC		jmp	AlignDone			;2
BTMB		bit.b	#0x08,		&P1IN		;4 record data bit for synccheck (.X.. capture)
		rlc.b	R14				;1 feed data into synccheck
		nop					;1
		nop					;1
		nop					;1
		jmp	AlignDone			;2
AlignDone	bit.b	#0x08,		&P1IN		;4 record data bit for synccheck (..X. capture)
		rlc.b	R14				;1 feed data into synccheck
		mov.b	#10,		&UCA0BR0	;4 Divider for SMCLK to 10-1 capture for data input
		bit.b	#0x08,		&P1IN		;4 record data bit for synccheck (...X capture)
		rlc.b	R14				;1 feed data into synccheck
		cmp 	#0x0B,		R14		;2 Check synccheck pattern   (....1011)
		jne	NOJOY				;2 if Bad, call nojoy
		bic.b   #0x20,		&P1IFG		;4 reset interrupt flag
		bis.b	#0x01,		&IE2		;4 Enable recieve interrupt
		reti

here is a flow diagram i tried to describe how it branches to delay the signal (block heights set to command execution time)

post-7036-0-33282100-1355280674_thumb.jpg

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