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spirilis

My time with the Renesas RX

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What I read was on wikipedia. Only read to the part where it was mentioned it was a Japanese company, and they were a major player in the cell phone industry. ( or something to that effect ). Thing is, if they do this much business, how on earth could they go bankrupt ? Maybe they're feeling the US economic heat all the way over in Japan ?

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Earthquake, flood, competition from Samsung, etc..

 

http://dealbook.nytimes.com/2012/12/10/japanese-manufacturers-bail-out-renesas/

That summed it all up nicely.  Didn't realize they were hit so badly by the earthquake... and other companies like Canon, Nikon got involved with the bailout too.  I guess the Japanese just have their own semiconductor & microcontroller ecosystem over there, and Renesas happens to be the one supplying it all...

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I do understand the earthquake hit Japan hard. But I am not sure what others think,  I personally tend to think Japanese make really good electronics stuff. So just based on the assumption everyone thinks like I do ( scary thought ), you might think they would bounce back fairly quickly. But apparently not. Granted, other areas of the world are not making things any easier by devaluing the market . . .

 

Anyway, I ordered a kit, the order is still open. We'll see if I get one. I have to admit, the kit looks pretty nice.

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Yeah with any luck the company will be profitable in a few years... I also agree about the Japanese making nice electronics.

 

I ordered my kit and forgot about it until like 3wks later when I suddenly got an email with shipment notification, and it arrived next day...

 

Sent from my C3PO via Tapatalk

 

 

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Yeah.  Give it about two weeks.  As long as you don't use a "free" email address, it probably won't be rejected.

 

You get an email that it shipped and they ship next day after waiting 2 weeks.

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My experience too.

I was hesitant about using my *mail.com address so I used my hardly-ever-used and fairly obscure company email address.

Nothing heard for couple weeks then received notification it shipped and had it the next day. It was shipped 2 day express.

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I used my gmail email. It is all I use, and I have had it . .well i can not remember how long. I have over 10GB of storage on it if that says anything. My buddy has a web/ email server, I suppose I could have set up and alias but meh .  .why. 

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Eh well, random note- Got closure on my DAC issue.  Turns out there's a pullup resistor somewhere on the board connected to that pin-

 

Hi Spirilis,

the reason is the load of the pull-up resistor R55 of 5.1kOhms at the DA1 output and the internal source impedance of 3.6kOhms inside the RX's DAC.

In the zero volt output case the voltage drop over the internal source resistance is 3.6kOhms/(3.6kOhms+5.1kOhms) * 3.3V ~ 1.36V.

Best regards

Ralf

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Also, that RX621/RX62N group datasheet is such a dry, overly verbose & structured, boring read.  Reminds me of english class back in high school.  Alas, for when I do finally start writing RSPI code, I soldered some male headers on the expansion headers on the RDK board so I can hook up my Saleae logic analyzer and see.  Somehow that feels more badass than twiddling LEDs ;-)

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Somehow that feels more badass than twiddling LEDs ;-)

 

Definitely higher geek points, especially if it's a real Saleae, and not one of the cheap knockoffs like mine.

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Yeah it's a real one, the Saleae Logic16 (splurge I made last May)...

 

Anyway, rather than watching the super bowl (I don't care about sports), I got RSPI working!  Used the Saleae to figure out why my SCLK/MOSI pins weren't doing anything, then hooked up an nRF24L01+ and used the onboard LCD display's backlight as an indicator whether things were working right (lol).

 

RSPI is a very powerful peripheral, it can be driven like a normal SPI device in what they call "clock synchronous" mode (3-wire SPI), the implication being that *you* are driving the devices' Chip Select line manually, or the RSPI driver has 4 Slave Select Lines that it can manage by itself.  The configuration is a bit verbose & hard to follow, and the RSPI chapter didn't seem to mention a few I/O port-related registers you had to configure ahead of time too.  But after figuring it all out, I have a fairly decent grasp on how it all works.

 

RSPI supports 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24 and 32-bit SPI transfers and also allows you to stuff multiple frames into the SPDR register, configuring how many frames get transferred before sending an interrupt/etc.  It also supports some alternative setups, like Multi-Master mode, Parity bits, and an Open-Drain variant.  There is a mode-fault detector (to discover if things are wired wrong I guess) and several other features.

 

In this instance, to keep things simple, I used 16-bit SPI to write & read the config registers from a nRF24L01+ transceiver, stuffing the command in the upper 8 bits and either the register value in the lower 8 bits (for writes) or zeroes for reads.

 

The program first powers up the transceiver (CONFIG: PWR_UP=1 EN_CRC=1), then verifies one of the bits in the CONFIG register (CRCO=0), then reads the SETUP_AW register to verify that it's valid and the address width =  5 bytes.

No IRQs use, but there are several available and you have to go through the general dance (clear IRQ, set IRQ priority, enable IRQ) to use them.

 

I'm not using the sequencing here, that's a feature that's very unique and DMA-driveable; you can set up 8 different SPI command modes, which each can specify different timings, bitrates, frame sizes, etc. and then tell the RSPI peripheral to walk through each command config with each subsequent write to SPDR.  The interrupts driven by the data transfers can trigger the DMA controller to write the next piece, etc. so you could, in theory, create a whole dance of SPI communication between several peripherals, pre-load the data in RAM somewhere, and let the DMA controller drive the whole entire process (pulling the chip select line low for device #1, sending the burst of data & transferring the results to a designated spot in RAM while pulling dev#1's chip select line high, then trigger the DMA transfer of more data which advances the command pointer to the next device, pulling its chip select line low & bursting the data, etc)

 

So without any more verbosity, here's my code:

 

hardware_setup.c

void HardwareSetup(void)
{
	SYSTEM.SCKCR.BIT.ICK = 0x00;  // ICLK = 96MHz
	SYSTEM.SCKCR.BIT.PCK = 0x01;  // PCLK = 48MHz
	SYSTEM.SCKCR.BIT.PSTOP1 = 1;
	SYSTEM.SCKCR.BIT.PSTOP0 = 1;

	PORT2.DDR.BIT.B1 = 1;
	PORT2.DR.BIT.B1 = 0;   // Shut off that distracting LCD backlight

	MSTP(RSPI0) = 0;  // Power-on RSPI0

	PORTC.DDR.BIT.B6 = 1;  // MOSIA-A output
	PORTC.DDR.BIT.B5 = 1;  // RSPCKA-A output
	PORTC.DDR.BIT.B4 = 1;  // SSLA0-A output

	PORTC.DDR.BIT.B7 = 0;  // MISO = input
	PORTC.PCR.BIT.B7 = 0;  // Pullup resistor off
	PORTC.ICR.BIT.B7 = 1;  // Input schmitt-trigger

	IOPORT.PFGSPI.BIT.RSPCKE = 1;  // RSPI0 RSPCK enabled
	IOPORT.PFGSPI.BIT.MOSIE = 1;   // RSPI0 MOSI enabled
	IOPORT.PFGSPI.BIT.MISOE = 1;   // RSPI0 MISO enabled
	IOPORT.PFGSPI.BIT.SSL0E = 1;   // RSPI0 SSL0 enabled
}

 

Finding out about those IOPORT.PFGSPI registers was rather random & frustrating.  Such a non-intuitive way to name/organize things.  These basically correspond to what we think of as P1SEL, P1SEL2, P2SEL, P2SEL2 btw.  They configure whether particular pins of a peripheral are attached to the actual pin.  One cool thing is a lot of the peripherals on the RX have 2 locations where their pins can reside; one of the bits in the IOPORT.PF* registers toggles that (and if you look at the pin diagram for the chips, you see stuff like RSPCKA-A, MISOA-A, MOSIA-A, SSLA0-A ... RSPCKA-B, MISOA-B, MOSIA-B, SSLA0-B; the -A and -B are alternate locations for the RSPCK, MISO and MOSI lines for RSPI0 ("A"))

 

Here's my main (rspi.c):

int main(void)
{
	uint8_t retval;
	uint32_t i;

	for (i=0; i < 12000000; i++)  // dummy pause
		;

	// Init RSPI
	RSPI0.SPCR.BYTE = 0;  // RSPI initialize mode
	RSPI0.SPPCR.BYTE = 0;
	RSPI0.SPBR = 1;  // Bitrate = PCLK/4, 12MHz
	RSPI0.SPDCR.BYTE = 0;  // SPDR accessed in words, only 1 frame in SPDR.
	RSPI0.SPCKD.BYTE = 1;  // Delay 2xRSPCK before transmitting (after SSL0 assert)
	RSPI0.SSLND.BYTE = 0;  // Default 1xRPSCK delay before de-asserting SSL0
	RSPI0.SPND.BYTE = 0;  // Haven't figured out what this is for.
	RSPI0.SPCR2.BYTE = 0;  // Not using parity
	RSPI0.SPCMD0.WORD = 0;
	RSPI0.SPCMD0.BIT.SPB = 15;  // 16-bits per frame
	RSPI0.SPCMD0.BIT.SCKDEN = 1;  // Actually make use of SPCKD value.
	RSPI0.SPCR.BIT.MSTR = 1;
	RSPI0.SPCR.BIT.SPE = 1;  // Showtime!

	// Power up the nRF24L01+ chip
	RSPI0.SPDR.WORD.H = (0x20 << 8) | 0x09;  // Write CONFIG, EN_CRC, PWR_UP
	while (!RSPI0.SPSR.BIT.SPRF)
		;
	retval = (uint8_t) ((RSPI0.SPDR.WORD.H & 0xFF00) >> 8);
	// retval now contains the contents of the STATUS register.
	RSPI0.SPDR.WORD.H = 0x0000;  // Read CONFIG register
	while (!RSPI0.SPSR.BIT.SPRF)
		;
	retval = (uint8_t) (RSPI0.SPDR.WORD.H & 0x00FF);
	if (!(retval & 0x04)) {
		PORT2.DR.BIT.B1 = 1;  // Turn on LCD backlight indicating we're OK!
	}

	RSPI0.SPDR.WORD.H = (0x03 << 8);  // Read SETUP_AW to validate this is an nRF24L01+ functioning
	while (!RSPI0.SPSR.BIT.SPRF)
		;
	retval = (uint8_t) (RSPI0.SPDR.WORD.H & 0x00FF);
	if ((retval & 0xFC) != 0 || (retval & 0x03) == 0) {
		PORT2.DR.BIT.B1 = 0;  // Turn off LCD backlight indicating we have an error here
	}
	if ((retval & 0x03) != 3) {  // Turn off LCD backlight if address width != 5
		PORT2.DR.BIT.B1 = 0;
	}

	RSPI0.SPCR.BIT.SPE = 0;  // Disable RSPI
	while(1)
		;

	return 0;
}

 

 

The SPDR register is huge, and configurable; it's either 64-bits or 128-bits depending on whether SPDCR has Word access or Long Word access enabled.  Since we're doing MSB-first, we have to store our bytes in the upper word (convenient union RSPI0.SPDR.WORD.H and L correspond to the upper and lower 32-bits).  I'm guessing the RSPI device accesses frames in terms of words, so for example even though we're doing a 16-bit transfer we don't have to shift the 16 bits to the upper 16 of RSPI0.SPDR.WORD.H, we can store it in the lower 16 bits, it looks at the WORD.H 32-bit value as a single frame and only transmits the lower N bits of it (where N is the frame size configured in SPCR.SPB).

 

Anyway, that just shows how you can stuff a whole lot of shit into the SPDR register, particularly in LongWord mode, and have it all burst out at once without the CPU having to intervene to keep sending bytes.

 

More to come here though, as I'd like to produce a simple application that sends packets over the nRF24L01+ to periodically flash an LED on one of my LaunchPads.

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Actually doing an nRF24L01+ library for the RX now... dragging my feet a bit but I got the game plan together.  Quite similar to my msprf24 lib, it'll be called "rxrf24".  Gonna get this finished up before playing with it any more.  That way I actually have something usable...

 

The next task beyond that will be to figure out the RPDL library from Renesas, and port it to that (since it's supposed to be the "one true" way to interface with their MCUs' hardware...)

 

No timeline or priority on that though ;)

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