Jump to content
Sign in to follow this  
alsenin

Booster pack interfaces and API standard

Booster packs intercompatibility  

11 members have voted

You do not have permission to vote in this poll, or see the poll results. Please sign in or register to vote in this poll.

Recommended Posts

Hi there!

 

Time goes, booster packs becomes more and more but pins of LP are not. May be necessary to think about standards of interfaces to be able to stacking any existing BP's to LP? Standards not for TI but as sign of good manners on 43oh. For example using SPI or I2C instead the UART and configurable lines for IRQ's and CS'es. Bridge SPI<->UART is only an additional cheapest MPS430G2 on BP. In benefits of this solution is possibility placing an API functions on this chip.

 

What are you think?

Share this post


Link to post
Share on other sites

I think at least some summary of which pins are used by different boosterpacks would be nice. I tend to look mainly at the RF pack for compatibility, but it would be good to be able to take others into account also.

Share this post


Link to post
Share on other sites

Or by standard all booster packs use solder jumpers, requiring you to select which pins to use, or having 6mil wire on the defaults that you can cut and solder what you want... Like was done with my LCD one. You can stick that on top of almost anything :)

Share this post


Link to post
Share on other sites

Agree with SA, every BP should give you option for at least selection pins, SPI could be shared and fixed (UCB0.)

Also, API should only apply to 20pin chips. This way you can use P2.x for selection and have all remaining P1.x for analog use, timer functions, etc.

P2.0 could be LCD select (there will most likely be only one LCD BP.)

P2.1 could be R/W, D/C, or similar feature select (FS,) not to be used for CS.

P2.2 BP2 select

P2.3 BP3 select or FS2 (I don't think you will stack more than 3 BPs.)

 

P1.5, P1.6, & P1.7 reserved for SPI/I2C

P1.1, P1.2, & P1.4 could be reserved for UART/secondary SPI

Share this post


Link to post
Share on other sites

Here's another idea, MSP430 Universal Booster Pack API.

Since there are not that many BPs yet (relative to other platforms,) how about designing a new standard, similar to LP but not based on chip's layout (like LP and FraunchPad is.) It would be function and pin based, so you know that the SPIA is on those 3 pins, SPIB on those, P1.0 on this one, and A0 on another.

This way, you could design a BP for any development board, and design development board that will work with all BPs.

For the existing BPs, DBs, and LP, an adapter board could be created.

The number of pins would most likely require double row headers, but if you put function pins on the outside rows, BP could have single row headers only. The port pins could be abandoned completely, leaving only function pins (similar to Arduino's digital pins,) or could be accessible via another, side header.

Share this post


Link to post
Share on other sites
Here's another idea, MSP430 Universal Booster Pack API.

Since there are not that many BPs yet (relative to other platforms,) how about designing a new standard, similar to LP but not based on chip's layout (like LP and FraunchPad is.) It would be function and pin based, so you know that the SPIA is on those 3 pins, SPIB on those, P1.0 on this one, and A0 on another.

 

I like that idea!

Share this post


Link to post
Share on other sites

Some pins on the dev board would be configurable, like CS1, CS2, etc. Things like SPIA, SPIB, UART, might not. For example 2553 board would have RXD and TXD hardwired. Some restrictions will be needed, like SPIB is the main SPI and you cannot use both SPIA and UART at the same time for example. Analog inputs will require some thought.

Share this post


Link to post
Share on other sites

I definitely think that supporting stacking boosters is needed. I've had a couple of instances where I'd like to stack boards and haven't been able to because of CS pins. I'm looking into doing a project that would have Ethernet, Bluetooth and an SMD ProtoPad - it would be nice to be able to throw an LCD on top as well, but I'm pretty sure my LCD booster has a conflict.

 

Here's my 2 cents (not sure if they can all be accomplished)

 

For SPI boosters -

the ability to choose between USCI A and B (In case you want I2c which I believe is only available on B)

The ability to pick a couple of CS pins (at least 2-3 options) using solder jumpers - there's probably a limit to the max # of BP that could realistically used in a project.

 

SA's solution of traces that can be cut, and pads for jumpers is a pretty good solution. I'm assuming it would make routing easier on more complicated boards, but still gives me a way to re-route the pins if needed.

 

Also - some of the BP's have pins clearly labeled - it would be awesome if that was a standard as well. It's nice to be able to pick up a BP and see at a glance which pins are used.

 

I do think it's reasonable to have some pins reserved for certain functions (as RobG suggested) - although I'm having a hard time thinking of anything else other than an LCD that could be categorized as being easily limited to 1 pin. Still - it might be nice to have the option of an extra CS pin in case someone wants a dual-display for some reason.

Share this post


Link to post
Share on other sites

I think having a standard is nice, but what TI drew up seems a bit constraining in the wrong places. For example:

 

-They don't specify any constraint on thickness of a boosterpack. Perhaps there isn't one, but I know that for the AC-powered AC-relay/SCR/TRIAC controller I'm making, you likely won't be able to stack anything on top because of the component heights.

 

-Why would they bother to limit the maximum height dependent on whether or not the 3 pin GND/GND/VCC header J3 is used? This seems arbitrary, because if I really wanted to make use of the space, but I don't really need the J3 connection, I may decide to "need" it anyway just to be compliant. Seems odd...

 

-Likewise, why spec the maximum height dependent on the BoosterPack pin count? My board needs a good bit of space to hold everything, so...I guess I chould go ahead and label it as an 80 pin-compatible device to get the extra height, even though I don't really need the 80 pins. If they are simply trying to keep the top of the LP accessible, yet maintain compatibility between an 80pin BP and a 20 pin LP, then the accessibility is defeated anyway because the top of the 20 pin LP can get covered up by an 80 pin BP.

 

-Is stacking on the back side of the LP allowed? This may be preferred if you have a BP that uses J3 but you don't want to cover up switches S1 and S2.

 

-Seeedstudio and Iteadstudio offer 5cm x 5cm max boards, as well as 5cm x 10cm max boards. The BP dimensions stated in TI's wiki have a max height slightly less than 5cm (20 or 40pin) and 10cm (80 pin), which would mean that to meet compatibility guidelines, I'd be shortchanging myself some board space that I pay for anyway. There may not be a whole lot of BPs that attempt or need to utilize as much space as you pay for, but for those that do (like mine) it just seems arbitrarily limiting.

Share this post


Link to post
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

Sign in to follow this  

×
×
  • Create New...