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YABB - Breadboard Booster on steroids


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YABB - Yet Another Breadboard Booster (this time on steroids)   Launchpad Booster integrated breadboards are undoubtedly very handy for learning and experimentation. However, there is no denying the

Here is the finished prototype board:     Note the jumpers in the 'Program' state. Move them to the left if you wish to use those MSP pins in your project.

OK, here's the schema:     and the laid out board:  

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Yes. From memory, the ISE package has everything you need, but it has been a while since I set up my toolchain. I will revisit this and produce a set of setup steps before we get the boards on offer.

 

Yes, they do harvest your email address. The development tools must cost them a fortune to develop, so I felt it was a more than fair exchange. They do send you the odd newsletter but no more than that.

 

Alternatively, you could try creating a tool chain based on web services. I think that is what the Xilinx Web Pack is and there is also plunify.com.

 

I might add, this tool suite also includes a hardware simulator that simulates your design before you download it to the CPLD. It is a pretty amazing bargain for only $0.00.

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  • 3 weeks later...

Hi again,

 

So I got the boards back from Seeed. They look great ...

 

... if it wasn't for a dumb design mistake I made.

 

I tied JTAG_TDO to ground and it is needed by the programming algorithm to confirm that the CPLD received the correct programming commands. What was I thinking.

 

They're not quite coaster material though. Two cuts and two straps should have them running. I'll be ordering parts for this at the end of the week. Let me know if you are interested in getting one of these prototypes. Since I borked the design, they'll be going for free :-).

 

In other progress, I have one of these parts on a breakout board, so while waiting for the boards I was able to follow up on cde's suggestion to have a pass through programming tool. In fact, this turns out to be the only option. I had forgotten how big the xsvf files are used to program these parts. The byte array would not fit in the flash of a msp430g2553.

 

I implemented the host end as an Eclipse plugin because that is what I use for msp development. I will publish a link to the source for this when we get some boards running. It will be pretty simple to port it into a standalone java tool, or even to another language. It just opens a file and dumps it to the msp430 serial port thru USB. It runs at 9600 baud so you will need a Launchpad that can be configured for the hardware uart. The programming process takes 2 minutes for the 9572 part.

 

Next up, I remembered that I had one of these parts implementing an 8 channel logic analyser at one point. All that was required was a fast SRAM to capture the transitions. The host front end was based on the sump project:

 

http://www.sump.org/projects/analyzer/

 

I'll dig out all the source for this if there is demand.

 

Finally, I have started on a new version of this board which uses the QFP100 package. When I reviewed the documentation, I was excited to see that the QFP100 XC9572XL and XC95144XL parts share the same pinouts, so the board will be able to be built with either chip. Given this added flexibility, I think this may be the one to go with.

 

Let me know what you think.

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Yes, CPLD's are pure digital. If you wanted to use the MSP built in ADC you'd want to bring that pin out before the CPLD. You could easily do that using the long pin connectors available in the store.

 

Alternatives are that you could use the CPLD to control an external ADC to achieve sample rates up to around 70 Msps. Depending on the sample rate, you might again need an external SRAM.

 

Given that these boards are going to need cuts and straps, I was thinking of pre-building them, but if anyone feels like giving SMD soldering a shot you can have a bare board.

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Well, that one is in a SOP, so you couldn't just pop it into the breadboard. You'd need to stack another board on top instead, but the CPLD could drive it for sure.

 

If you could find another high bit count ADC in a DIP package you could use it directly without another board (getting harder to find though, I know).

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Actually, looking more closely at that ADC it uses SPI, so why not just hook it to the MSP directly?

 

CPLD's come into their own for interfacing to IO pin heavy devices, such as those with 16 (or even 8) bit ports. The CPLD can read the state of the pins and convert them into an SPI stream for example.

 

In the case of this chip, that's already done for you.

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  • 2 weeks later...

Finally got parts and made one of these and it works great.

 

I also set up the Xilinx development flow on Linux and proved it works (I only used the windows version in the past).

 

For those of you on Linux, Xilinx only supports SUSE 11 and RHEL 5 and 6. Since neither of these are free, I tried OpenSUSE 11 which worked fine (OpenSUSE12 had dynamic library conflicts). A Fedora distro from around the RHEL 5 era might work, but I did not try it. For other distros, you'd be on your own though I'll help if I have the knowledge.

 

To whet your appetite here is some simple Hello world VHDL:

 

entity light_LED_PB is Port (S2: in STD_LOGIC:='H'; LED1 : out STD_LOGIC:='0';

LED2 : out STD_LOGIC:='0');

end light_LED_PB;

 

architecture Behavioral of light_LED_PB is

begin

 

LED1 <= S2;

LED2 <= not S2;

 

end Behavioral;

 

This will alternate between the green and red Launchpad LED's when Launchpad button S2 is pressed. For it to work, you need to set the host MSP430 to all inputs with pull-up resistors enabled (the loader program does this when it completes). It also works with no processor installed* (just to prove its really the CPLD that is doing the work).

* You do need a pull-up resistor on Port 1.3 in this case

 

You use a User Constraint File to tell the Xilinx tool chain which pins correspond to which signals in the design, so:

 

#PINLOCK_BEGIN

 

NET "S2" LOC = "S:PIN40";

NET "LED1" LOC = "S:PIN18";

NET "LED2" LOC = "S:PIN39";

 

#PINLOCK_END

 

... does this for you. You then build it using the Xilinx tool chain and use an MSP430 program and Java based front end to load the resulting xsvf file into CPLD. That's it! That's how easy it is to design and program this part.

 

I have enough parts to make another 8 or so of these boards. Because these are prototype boards and have a strap on them, I'd be willing to make a few available for free if anyone is interested in playing with an early version. Of course, I'll be making the support software I have created available, including the CPLD programmer for the MSP430 and the Java front end.

 

I have the final board routed and ready to go, but I'd like to play around with this version and get some feedback before making more boards. The final board will have the TQFP100 package which provides more I/O and offers a choice of 72 and 144 macrocell devices.

 

Let me know if you'd like one of these prototypes. I would be grateful if some of those who take me up on this offer would help write some tutorial materials and document tool set up for different host OS's etc.

 

Let me know what you think. Pictures coming soon.

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And here is the underside with the CPLD:

 

post-27273-135135559509_thumb.jpg

 

Oh my! The camera makes those CPLD solder joints look ugly. In real life they're just fine. :)

 

Note the ugly strap which fixes the mistake I made in the design. Production boards won't have those of course.

 

I put some hot glue on the strap to make sure the pin doesn't break off the CPLD.

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