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24x16 text on VGA using Launchpad w/ G2553


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This is derived from NTSC/PAL video text display using launchpad. video_vga.asm is a drop in replacement for video.asm.

 

post-2341-135135545577_thumb.jpg

 

The sync timing is for 640x480 60 Hz VGA mode. A 330 ohm resistor must be used on all video lines (R/G/B) because they are analog signals with a max allowed voltage of about 1 volt. Only one of the R/G/B lines can be driven directly from the MSP430 due to current limitations. A buffer such as 74AHC125 could be used to drive all three if desired.

 

Wiring

Gnd ------------ Ground [5, 6, 7, 8, 10]
P1.5 ----------- Vertical Sync [14]
P1.6 ----------- Horizontal Sync [13]
P1.7 ---[330]--- Video out (R [1], G [2] or B [3])

 

video_vga.asm

;

; Copyright © 2011, 2012 Kevin Timmerman

;

; This program is free software: you can redistribute it and/or modify

; it under the terms of the GNU General Public License as published by

; the Free Software Foundation, either version 3 of the License, or

; (at your option) any later version.

;

; This program is distributed in the hope that it will be useful,

; but WITHOUT ANY WARRANTY; without even the implied warranty of

; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

; GNU General Public License for more details.

;

; You should have received a copy of the GNU General Public License

; along with this program. If not, see .

;

 

.cdecls C, LIST, "msp430g2553.h"

 

.text

.def video_init ; void video_init(void); - Initialize video generation

.def field_timer ; extern int field_timer; - Decremented at each vsync

.def vblank ; Vertical blanking flag

.ref text ; Text buffer

.ref font ; Font 8 x 12, grouped by row

;

;

.bss sync_state, 2 ; Sync state

.bss sync_lines, 2 ; Lines until next sync state

.bss video_state, 2 ; Video generation state

.bss vblank, 2 ; Vertical blanking flag

.bss field_timer, 2 ; Decrement at vsync

.bss text_ptr, 2 ; Text buffer pointer

.bss font_ptr, 2 ; Font pointer

 

 

; --- Ideal VGA 640 x 480 60 Hz Timing ---

; Pixel clock 25.175 MHz

; Horizontal 31.47 kHz (pix / 800, negative sync)

; Vertical 59.94 Hz (pix / 420000, negative sync)

; - Horizontal timing (line)

; Scanline part Pixels Time [

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Using the more powerful F5418A at 25 MHz allows the full 640 x 480 resolution to be used for up to 80x40 text display.

This requires sending SPI data at 25 Mbps - that is one byte every 8 clock cycles. Each byte requires reading the text buffer, font table lookup, and SPI tx. There is no time to check SPI status or to decrement and test a loop counter. An unrolled loop with exactly 8 cycles per byte is used to make this work.

 

       .loop 80                        ;
       mov.b   @R10+, R15              ; Get a text char
       add     R12, R15                ; Add font pointer
       mov.b   @R15, &UCB0TXBUF        ; Output font data to SPI
       nop                             ; Exactly 8 cycles per byte
       .endloop                        ;

 

Lower horizontal resolutions use more conventional coding. Still have some work to do on this before making code available.

 

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  • 8 months later...

oPossum, 

 

Being a hardware newb myself, this leaves me to wonder if it would be possible to do something like scan line interleave with multiple SPI channels.

 

Originally I was thinking along the lines of VESA bank switching but that wouldn't help performance wise.

 

Either way, some of this stuff you do just boggles the mind lol.

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