Setting up the DCO properly

[JMac3108 0]

Hi guys. I'm new to the forum and have a question that I hope someone can help me with. I'm using an MSP430G2231 on a LaunchPad development board. I setup the DCOCTL and BSCCTL1 registers to change the DCO clock frequency from the default 1MHz to 10MHz. This worked fine but the clock is jittering badly (viewed on an oscilloscope) and it appears that the clock modulator is causing this even though I turned it off. My code is shown below. Thanks.

 

// Setup DCO to generate 10MHz clock, (RSEL,MOD) = (14,3)

BCSCTL1 |= (RSEL1 + RSEL2 + RSEL3); // RSELx = 14

BCSCTL1 &= ~(RSEL0);

DCOCTL |= (DCO0 + DCO1); // DCOx = 3

DCOCTL &= ~(DCO2);

DCOCTL &= ~(MOD0 + MOD1 + MOD2 + MOD3 + MOD4); // Clock modulation off

[nuetron 64]

Did you calibrate the DCO? http://www.43oh.com/forum/viewtopic.php?f=10&t=239

[JMac3108 0]

Nuetron,

 

No, I didn't calibrate it. I wasn't interested in absolute accuracy of the DCO so I wasn't worried about calibrating it at this point. With the settings I used the DCO is close enough to 10MHz for my purposes. However it is jittering all over. Much more than could be blamed on not being calibrated. It really appears as if the clock modulator is running even though I set all the MODx bits low.

 

Have you seen this before and was it caused by lack of calibration? Thanks.

[pabigot 355]

Some ideas that may or may not be useful:

 

Recommended practice for setting the DCO in the BCS+ is to clear DCOCTL first; thus:

DCOCTL = 0;
BCSCTL1 = XT2OFF | 14;
DCOCTL = 3 * DCO0;

Instability may result if the DCO has an invalid intermediate configuration as a consequence of piecemeal setting of the registers.

 

Check whether the DCO source also exhibits jitter. You didn't provide a BCSCTL3 setting, so presumably it's at the default configuration for an external crystal, though that might not actually be happening if you don't have one or didn't also configure the XIN/XOUT pins (see this thread regarding validating the crystal behavior).

 

Check for oscillator faults represented in BCSCTL3.LFXT1OF and IFG1.OFIFG.

 

Check whether the same jitter is present at lower RSELs. It may be that RSEL 14 is simply beyond what your device can handle.

 

Also check for jitter on ACLK and SMCLK by selecting the peripheral function to bring them out to P1.1 and P1.4, respectively, if that's not how you're detecting the jitter on DCOCLK itself.

 

Unlike the UCS and FLL+ on other systems, it doesn't seem that the BCS+ modulator has a feedback capbility to reconfigure itself, so as long as the low bits of DCOCTL read back zero I'm doubting the jitter is due to the modulator.

[pabigot 355]

Check whether the DCO source also exhibits jitter. You didn't provide a BCSCTL3 setting, so presumably it's at the default configuration for an external crystal, though that might not actually be happening if you don't have one or didn't also configure the XIN/XOUT pins (see this thread regarding validating the crystal behavior).

That, of course, is baloney, since as I look at the BCS+ schematic in figure 5.1 of the 2xx user's guide more closely, DCOCLK does not have an external source. In which case perhaps there's no reason to expect it to ever be stable.

[JMac3108 0]

I'll try to respond to everything ...

 

I'm looking at SMCLK on P1.4, thats where I'm seeing the DCO clock jitter.

 

Yes, the jitter occurs at lower frequencies.

 

There is no external source, no XT2 crystal. Just using the internal DCO oscillator.

 

I do not believe that the DCO is inherently unstable. I'm seeing a LOT of jitter and its hard to believe the internal DCO oscillator is that bad. I'll get in touch with TI tomorrow and ask them about it. Thanks everyone for the comments. Keep them coming!

[JMac3108 0]

Oh, and based on something I read in a TI app note I added a delay before changing the clock settings to make sure that VCC is stable first. It didn't help of course.

[JMac3108 0]

It was mentioned that if I read back zeros for the MOD bits then its not likely that the clock modulation is running and causing my jitter.

 

I'm using CCS and don't have it all figured out yet. When debugging I open a register watch window and have all the peripheral registers showing in it. I also clicked on the "continuous refresh" button. But all the registers say "unable to read" and if I double click on them to show the individual bits, they all read zero. Any ideas on what I'm doing wrong? I would feel better if I could manipulate the MOD bits and see them change.

 

BTW, thanks for all the help. I'm new and haven't introduced myself yet. I'm an electrical engineer and most of my work has been in the analog realm - switching power supplies and such. I'm relatively new to the microcontroller world. I've written a few programs on the MSP430 but am still learning. I find that you really have to dig through the datasheet, users guide, and TI sample code to figure out how to set up the peripherals. In particualr the timer and ADC took me some time to get going. This is my first attempt at doing anything with the clock. As usual I though it would be simple and have already spent too much time on it.

[zeke 693]

JMac, have you gotten a hold of MSP430 Microcontroller Basics yet?

 

It's the defacto standard for learning the MSP430, IMO.

[JMac3108 0]

Zeke,

Yes, I have it and its great. Often its better than the TI documentation IMO.

[OppaErich 25]

JMac, have you gotten a hold of MSP430 Microcontroller Basics yet?

 

It's the defacto standard for learning the MSP430, IMO.

AFAIR there were only calibrated values used or I must have missed it completely. I'm trying to run a value line chip from DCO at ~8 MHz, don't know if I did it right. Is the clock available at some pin ? I would like to watch it with a scope.

[Rickta59 589]

I would like to watch it with a scope.

 

If you have a scope or a frequency setting on your digital meter, enabling the direction and selection bits will

output the SMCLK on P1.4 The code below shows that and some different measurements I did on an

msp430g2553 using the different no-modulated bit settings. These don't seem to jitter that much on the

chip I was testing.

 

@JMac3108, what kind of jitter are you experiencing? With the the 9.9MHz setting I used below I'm seeing

a fluctuation between ~9.914MHz - ~9.928MHz. It seems like that is less than 1%. I'm not using precision

instruments so this is probably bogus. Are you doing your testing with a bare launchpad, without any pins

connected? I'm not sure how this would affect it, however, that is my setup.

 

Thanks for starting this thread. I had a feeling that turning off modulation would result in a more

stable clock. Your threaded prompted me to do some digging. Setting the frequency and range

selection bits without modulations bits seems to make a much more stable clock compared to

using the modulated calibrated values. I think I'd rather have a stable clock I could measure than

one that is average and jumps all around.

 

Some of my results:

 

P1DIR |= BIT4; P1SEL |= BIT4;

#if 0
   // ~98.4kHz
   DCOCTL = 0;
   BCSCTL1 = XT2OFF | ( 0 << 3 | 0 << 2 | 0 << 1 | 0 << 0) ;
   DCOCTL = (0 << 7 | 0 << 6 | 0 << 5);
#endif
#if 0
   // ~172.4kHz
   DCOCTL = 0;
   BCSCTL1 = XT2OFF | ( 0 << 3 | 0 << 2 | 0 << 1 | 0 << 0) ;
   DCOCTL = (1 << 7 | 1 << 6 | 1 << 5);
#endif
#if 0
   // ~164.0kHz
   DCOCTL = 0;
   BCSCTL1 = XT2OFF | ( 0 << 3 | 0 << 2 | 1 << 1 | 0 << 0) ;
   DCOCTL = (0 << 7 | 0 << 6 | 0 << 5);
#endif
#if 1
   // ~286.75kHz
   DCOCTL = 0;
   BCSCTL1 = XT2OFF | ( 0 << 3 | 0 << 2 | 1 << 1 | 0 << 0) ;
   DCOCTL = (1 << 7 | 1 << 6 | 1 << 5);
#endif

#if 0
   // ~5.0MHz
   DCOCTL = 0;
   BCSCTL1 = XT2OFF | (1 << 3 | 1 << 2 | 0 << 1 | 0 << 0) ;
   DCOCTL = (0 << 7 | 1 << 6 | 0 << 5);
#endif

#if 0
   // ~9.9MHz
   DCOCTL = 0;
   BCSCTL1 = XT2OFF | (1 << 3 | 1 << 2 | 1 << 1 | 0 << 0) ;
   DCOCTL = (0 << 7 | 1 << 6 | 0 << 5);
#endif

 

-rick

[pabigot 355]

Thanks for starting this thread. I had a feeling that turning off modulation would result in a more

stable clock.

In fact, for the 5xx/6xx series there are some serious errata that make disabling the FLL pretty important. See this E2E thread.

[JMac3108 0]

I'm measuring SMCLK directly on the LaunchPad board - I don't have any additional circuitry attached yet.

 

I can't say how much the jitter is because the signal is moving so much I can't get a trigger on the scope. Usually with clock jitter you can trigger on the leading edge and see the trailing edge jittering. In this case if I set the scope on auto trigger I get an EYE diagram, if I set it on HF Reject I can see the clock but its moving all over. This definitely makes me think the modulation is on and is moving the frequency.

 

But, I set the MOD bits to zero in the DCOCTL register which should have turned off modulation. I finally figured out how to view the register in CCS while in debug and I verified that in fact I had set the bits to zero. (You have to HALT to see the register values - I was trying to see them while running).

 

I'm running out of ideas. I didn't have time today to contact TI and try to get an answer. Guess thats my next step.

[oPossum 1,083]

I can't say how much the jitter is because the signal is moving so much I can't get a trigger on the scope. Usually with clock jitter you can trigger on the leading edge and see the trailing edge jittering. In this case if I set the scope on auto trigger I get an EYE diagram, if I set it on HF Reject I can see the clock but its moving all over.

 

That is very similar to what I see with the Fraunchpad (MSP430FR5739). I can't get the scope to really sync well.

 

The G series chips seem reasonably stable. This is a G2553 with these settings for DCO:

DCOCTL 0x00

BCSCTL1 0x87

BCSCTL2 0x00

BCSCTL3 0x05

 

Looks like about +/- 3 ns jitter.

 

 

With the modulator set to 7, there are clearly two different clock periods in use.

 

 

16 MHz factory calibration.