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could not source MCLK form watch 32KHz crystal

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I'm failing to see why I could not clock the CPU of the msp430g2452 for 32KHz wath crystal. I'm observing the same behavior from two different launchpad boards with soldered  32Khz crystal (one tiny yellow crystal that came with the kit and cylinder bigger one); and with several different msp430g2452. I'm observing the 32KHz square on P1.0 when it set to output the ACLK. 

Seems that the MCLK is always clocked from DCO regardless of the SELM_[0-3] I'm trying to push to  BCSCTL2. 

I'm checking P2.1 output as it is software toggled in endless loop; it is 20 times slower than MCLK.

What am I missing? in the block diagram slau144 page 275 MCLK should source  DCO when set SELM_0 or SELM_1; or clock from LFXT1 when set SELM_2 or SELM_3.



#include  <msp430g2452.h>

int main(void) {

//   // ACLK 32KHZ SMCLK 1MHz MCLK 50Hz
//   P1DIR |= 0x11;                            
//   P1SEL |= 0x11;
//   P2DIR |= 0x01;    for (;;)     P2OUT ^= 0x01;   

  // ACLK 4KHZ SMCLK 130KHz MCLK 200Hz
  P1DIR |= 0x11;                            
  P1SEL |= 0x11;
    BCSCTL2 |= SELM_2;  // SELM_0 or SELM_1 or SELM_2 or SELM_3 has no effect on P2.0 output
  BCSCTL1 |= DIVA_3;
  BCSCTL2 |= DIVM_3;
  BCSCTL2 |= DIVS_3;
  P2DIR |= 0x01;    for (;;)     P2OUT ^= 0x01;   



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