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piranha32

msp430-g++ and interrupts

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Hello,

 

I have a problem with strange behavior of gcc compiler, which does not seem to generate interrupt vectors correctly. I tried to search for hints on the forum, but could not find any helpful information.

I have the following C code:

void __attribute__((interrupt(TIMER0_A0_VECTOR))) timer0_isr(void)
{
  //IMPORTANT !!!!!!!
  //Clear TAIV by reading it !!!!
  (void) TAIV;

  /* ... */
}

void __attribute__((interrupt(TIMER0_A1_VECTOR))) timer0_a1_isr(void)
{
  P1OUT ^= PIN0;
}

volatile int qq;
__attribute__((interrupt(USCIAB0TX_VECTOR))) void usci_tx_isr(void)
{
  qq=1;
  P1OUT ^= PIN6;
  IFG2 &= ~UCA0TXIFG;
}

__attribute__((interrupt(USCIAB0RX_VECTOR))) void usci_rx_isr(void)
{
  qq=2;
  P1OUT ^= PIN6;
  if(IFG2 & UCA0RXIFG)
  {
    (void) UCA0RXBUF;
  }
  IFG2 &= ~UCA0RXIFG;
}

Only the TIMER0_A0_VECTOR ISR contains meaningful code at the moment, and the other 3 procedures are just placeholders.

For some strange reason, the only ISRs which are linked in the executable code to the interrupt vector table are TIMER0_A0_VECTOR and TIMER0_A1_VECTOR:

Disassembly of section .vectors:

0000ffe0 <__ivtbl_16>:
    ffe0:       6c c1           bic.b   @r1,    r12     
    ffe2:       6c c1           bic.b   @r1,    r12     
    ffe4:       6c c1           bic.b   @r1,    r12     
    ffe6:       6c c1           bic.b   @r1,    r12     
    ffe8:       6c c1           bic.b   @r1,    r12     
    ffea:       6c c1           bic.b   @r1,    r12     
    ffec:       78 c4           bic.b   @r4+,   r8      
    ffee:       8e c4 6e c4     bic     r4,     -15250(r14);0xc46e(r14)
    fff2:       b8 c3 6c c1     bic     #-1,    -16020(r8);r3 As==11, 0xc16c(r8)
    fff6:       6c c1           bic.b   @r1,    r12     
    fff8:       6c c1           bic.b   @r1,    r12     
    fffa:       6c c1           bic.b   @r1,    r12     
    fffc:       6c c1           bic.b   @r1,    r12     
    fffe:       00 c0           bic     r0,     r0      

I must be doing something wrong, but I can't find where is the mistake.

Target CPU is MSP430G5553, and here is the information about the compiler:

$  ~/.platformio/packages/toolchain-timsp430/bin/msp430-g++ -v
Using built-in specs.
Reading specs from ~/.platformio/packages/toolchain-timsp430/bin/../lib/gcc/msp430/4.6.3/../../../../msp430/lib/msp430mcu.spec
COLLECT_GCC=~/.platformio/packages/toolchain-timsp430/bin/msp430-g++
COLLECT_LTO_WRAPPER=~/.platformio/packages/toolchain-timsp430/bin/../libexec/gcc/msp430/4.6.3/lto-wrapper
Target: msp430
Configured with: ../../gcc/configure --enable-languages=c,c++ --disable-nls --target=msp430 --prefix=/home/robertinant/opt/mspgcc_energia --with-pkgversion='MSPGCC 20120406 (With patches: sf3540953 sf3559978)'
Thread model: single
gcc version 4.6.3 20120301 (mspgcc LTS 20120406 unpatched) (MSPGCC 20120406 (With patches: sf3540953 sf3559978)) 

Has anybody encountered similar problems?

EDIT: Moving void before __attribute__ has no effect.

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0000ffe0 <__ivtbl_16>:
ffe0: 6c c1
ffe2: 6c c1
ffe4: 6c c1
ffe6: 6c c1
ffe8: 6c c1
ffea: 6c c1
ffec: 78 c4 ;1
ffee: 8e c4 ;2
fff0: 6e c4 ;3
fff2: b8 c3 ;4
fff4: 6c c1
fff6: 6c c1
fff8: 6c c1
fffa: 6c c1
fffc: 6c c1
fffe: 00 c0 ;5

 

There are 5 vectors in that table

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There are 5 vectors in that table

Ah, thanks! Stupid formatting. That explains the mystery. I checked addresses for a couple of vectors, but I missed those in between.

The fifth one is the default power up vector, so I'm not concerned about it.

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