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Showing results for tags 'FIFO'.
Found 2 results
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Hi there! I've got a strange (to me) issue with UART flow control on LM4F120XL. For testing purpouse I use the UART1 both with FIFO enabled and disabled. When FIFO is enabled I use hardware flow control, when FIFO is disabled I'm trying to use the RX interrupt to perform software flow control (I assert and deassert RTS by code insider the interrupt handling routine). The thing is the I would like to test various RTS behaviours: 1) RTS off after 2, 4, 8, 12, 14 characters when FIFO is enabled 2) RTS off after every char when FIFO is disabled But what I see is that when FIFO is enabled (with
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I'm coding a module for using the UART in the Stellaris Launchpad. I want to use FIFOs. My problem is with the documentation. LM4F120H5QR datasheet states each UART has a 16x8 FIFO for Tx and another 16x8 FIFO for RX. But I can't find what is the FIFO width and what is the FIFO depth. Is the FIFO "16 bit x 8 elements", or is it "8 bit x 16 elements"? PS: Why UART FIFO isn't documented like for example the SSI FIFO. For the SSI FIFO, the datasheet makes it clear: "Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep"
