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Buy @ The 43oh Store. So I got a couple samples of the F5172 (has 5V-tolerant I/Os, 32KB flash + 2KB SRAM, Timer_D can run up to 256MHz with FLL) this past summer and had nothing to do with them. Original idea was to make an Arduino-variant since it has around 12 5V-tolerant I/Os, but I decided against that when I first read about TI's 40-pin XL standard. EDIT: Link to newest revision of this design: http://forum.43oh.com/topic/2828-msp430f5172-launchpad-xl/page-4#entry31194 Between last night and this morning I did some marathon CAD, and came up with my F5172 LaunchPad. Let me know what you think: (OSHpark mockup images, I'll most likely use Seeed and make them red.) Bottom: Notes: 1. The board includes "mount" headers (female headers pointing down) to plug into the Emulation layer on the MSP430 LaunchPad rev 1.5. As I understand it, TI does *not* support the use of the LP's SBW for programming or debugging F5xxx devices but I've heard it does in fact work, maybe with some limitations (on the E2E forums someone was complaining step-by-step execution didn't work). 2. The board includes the MSP-FET430UIF 14-pin header, SBW-only (and wired in accordance with slau278k's recommendations for SBW on F5xxx and F6xxx devices). A 3-pin jumper is there to select VCC TOOL (sourced from the FET tool) or external power. 3. To align with TI's recommendations for the 40-pin XL pin functions, some ports have been duplicated to more than one LP pin. There is a vertical bar next to the pin label if it's also used elsewhere in the 40-pin layout. 4. The device includes an FTDI FT232RL chip for the serial port. TXD and RXD LEDs are attached to CBUS0/CBUS1 and CBUS2-4 from the FTDI are broken out to a header. I now have headers in place to disable the TX/RX circuit from the chip. 5. An LDO TPS77333 regulator (similar to MSP430 LaunchPad) is included for providing 3.3V power off the 5V USB feed. LDO_EN lets you enable/disable this and LDO_RST connects the RESET line to the F5172's RESET so the LDO can keep the chip halted until the LDO has built up its output voltage. 6. LEDs on P1.7 and P3.6 (both PWM-able) have been included, I was thinking of using a white LED with P1.7 and blue LED with P3.6. 7. P2.7 is not broken out to any of the LP pins, so it's specially designated for the SW1 button which also has a hardware debounce circuit. Should be idle-high, active-low (low when pressed). 8. The 5V tolerant pins are enabled by switching the "VIO" header to 5V. 9. XTALs are on the bottom, there are footprints for a tuning fork crystal and a HF through-hole crystal with its load capacitors nearby. 10. AVcc exists on these chips so I set up an LC filter for it, L1 (10uH SMD) and C9 (10nF SMD). 11. The F5172 datasheet, page 33, note 3 has not been adhered to--if VIO jumper is set to 5V it will probably get power before the LDO has spun up the 3V3 rail. We'll see if that matters (I doubt it)...