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    gfleming1992 got a reaction from energia in faster adc sampling at 1 MHz clock speed   
    Water Rockets,
    Thanks for the help! By removing the ISR and optimizing the inner loop, I was able to maintain a sampling frequency of 51 KHz at 1 MHz clock speed:
    for(i =255;i!=0; i--) { //_delay_cycles (1); // delay program execution for 335 cycles //__bis_SR_register(CPUOFF + GIE); // LPM0, ADC10_ISR will force exit //q0=-q1-q2+value; q0 = ADC10MEM; ADC10CTL0 |= ADC10SC; q0+=-(q1+q2); q2=q1; q1=q0; } Regards, George
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    gfleming1992 reacted to USWaterRockets in faster adc sampling at 1 MHz clock speed   
    Yes, the ADC will run by itself, and would be off doing a sample while the CPU is waiting for the interrupt to signal the conversion is complete. If you take out the code that makes the CPU wait for the interrupt, you can use the CPU to do anything you like, while the ADC is busy. You could possibly get rid of the interrupts completely, and just start the ADC from your main loop, do your math on the previous reading, and then poll the ADC status bits to find out when the conversion was complete, then go back and start the next conversion and repeat this process.
    Another different idea you could try is to save the samples in memory instead of trying to process them in real time, and once you have 255 samples accumulated, you then process the stored conversions. From your code it looks like you only take 255 samples at a time, so this would potentially let you run the CPU much slower because the  CPU clock speed could be very slow and still manage to convert/store 255 samples at 51KHz.
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