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Everything posted by gfleming1992

  1. Water Rockets, Thanks for the help! By removing the ISR and optimizing the inner loop, I was able to maintain a sampling frequency of 51 KHz at 1 MHz clock speed: for(i =255;i!=0; i--) { //_delay_cycles (1); // delay program execution for 335 cycles //__bis_SR_register(CPUOFF + GIE); // LPM0, ADC10_ISR will force exit //q0=-q1-q2+value; q0 = ADC10MEM; ADC10CTL0 |= ADC10SC; q0+=-(q1+q2); q2=q1; q1=q0; } Regards, George
  2. Hi water rockets, I am able to approximate the 51 kHz frequency based on mathematical operations I am conducting in another portion of the code. Is there a way I can complete the mathematical operations for the previous sample while the next sample is being prepared in the ADC unit? If I use the method above, when I slow the clock frequency to 1 Mhz, my sampling frequency drops to ~30kHz. Thanks, George
  3. Hi guys, I am working on a university design project and I am running into an ADC10 sampling limit on MSP430G2553. For a number of reasons, I need to be able to sample and process an input signal at 51 KHz. I can do this with my current setup with a clock speed of 4 MHz. I would, however, like to bring this speed down to 1 MHz so I could run the uC at a lower voltage level. The following is my current code: #include <ctype.h> #include "msp430g2553.h" short value=0; long magnitude0 = 0, magnitude1 = 0; short q0=0,q1=0,q2=0; unsigned int sum = 0; char state0 = 0; char state1
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