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fatihinanc

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Posts posted by fatihinanc

  1. @@MSPLife

    I agree with @@chicken also,

     

    TI uses TPS series as there many low power LDOs in this family. LM series are old and not power efficient now.

    For exaple TPS782xx series. This LDO is only consumes 500nA with 150 mA load. This is very good value for a LDO.

    ST and other vendors have also similar LDOs but TI's is better one, I have ever seen yet.

  2. @@nickn

     

    You just need to set PMM registers and change the core voltage step by step. The code which given below sets the core voltage to correct value and also generates 25 MHz from LFXT1(32.768kHz). It is referenced from TI code examples.(MSP430F55xx_UCS_10.c) Only difference is ACLK = LFXT1, not REFO.

    void set25mhz(void)
    {
      P5SEL |= BIT4 + BIT5;                       // Select XT1
      
      // Increase Vcore setting to level3 to support fsystem=25MHz
      // NOTE: Change core voltage one level at a time..
      SetVcoreUp (0x01);
      SetVcoreUp (0x02);  
      SetVcoreUp (0x03);  
     
      UCSCTL6 &= ~(XT1OFF);                     // XT1 On
      UCSCTL4 |= SELA_0;                        // ACLK = LFTX1 (by default)  
      UCSCTL6 |= XCAP_3;                        // Internal load cap
    
      __bis_SR_register(SCG0);                  // Disable the FLL control loop
      UCSCTL0 = 0x0000;                         // Set lowest possible DCOx, MODx
      UCSCTL1 = DCORSEL_7;                      // Select DCO range 50MHz operation
      UCSCTL2 = FLLD_0 | 762;                   // Set DCO Multiplier for 25MHz
                                                // (N + 1) * FLLRef = Fdco
                                                // (762 + 1) * 32768 = 25MHz
                                                // Set FLL Div = fDCOCLK/2
      __bic_SR_register(SCG0);                  // Enable the FLL control loop
    
      // Worst-case settling time for the DCO when the DCO range bits have been
      // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
      // UG for optimization.
      // 32 x 32 x 25 MHz / 32,768 Hz ~ 780k MCLK cycles for DCO to settle
      __delay_cycles(782000);
    
      // Loop until XT1,XT2 & DCO stabilizes - In this case only DCO has to stabilize
      do
      {
        UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG);
                                                // Clear XT2,XT1,DCO fault flags
        SFRIFG1 &= ~OFIFG;                      // Clear fault flags
      }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag 
    
      UCSCTL6 &= ~(XT1DRIVE_3);                 // Xtal is now stable, reduce drive strength  
    }
    
    void SetVcoreUp (unsigned int level)
    {
      // Open PMM registers for write
      PMMCTL0_H = PMMPW_H;              
      // Set SVS/SVM high side new level
      SVSMHCTL = SVSHE | SVSHRVL0 * level | SVMHE | SVSMHRRL0 * level;
      // Set SVM low side to new level
      SVSMLCTL = SVSLE | SVMLE | SVSMLRRL0 * level;
      // Wait till SVM is settled
      while ((PMMIFG & SVSMLDLYIFG) == 0);
      // Clear already set flags
      PMMIFG &= ~(SVMLVLRIFG | SVMLIFG);
      // Set VCore to new level
      PMMCTL0_L = PMMCOREV0 * level;
      // Wait till new level reached
      if ((PMMIFG & SVMLIFG))
        while ((PMMIFG & SVMLVLRIFG) == 0);
      // Set SVS/SVM low side to new level
      SVSMLCTL = SVSLE | SVSLRVL0 * level | SVMLE | SVSMLRRL0 * level;
      // Lock PMM registers for write access
      PMMCTL0_H = 0x00;
    }
    
  3. Hello ARM-HQ,

     

    My name is Fatih. I am a student in Turkey.

    I have interested Embedded Linux Systems, FPGA's and Analog Electronics.

    I have developed several projects using MSP430, ARM, BeagleBone and BeagleBoard platforms.

    And I've used NXP's,TI's and ST's ARM Cortex M3 based boards.

     

    In my spare time, I worting some blog. This is my blog : www.fatihinanc.com

     

    (Sorry for my English)

    Thanks.

    Best Regards.

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