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andrea_mori

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  1. I was joking too, and I appreciate a lot your irony, "oxygen free copper wires facing towards Mecca" was fantastic! Now is more clear, I'm looking to avoid reading a thousand pages. As I understand I cannot use USB with my oscillator as the external clock, because USB interface requires multiple of 1 MHz clock, so I'll use the SD as the storage device. Thinking to the TDA1541A firstly... I have to replace the onboard 8 MHz HSE with mine 11.2896 MHz. I believe I have to desolder the 8 MHz crystal and a pair of capacitors, I'm not sure since I have no schematics of the Disco board I need a couple of timers: the TDA1541A supports 6.4 MHz maximum bit clock, so the first timer should divide by 2 the master clock frequency. This clock should be stopped after the 16 bit for each channel in simultaneous mode (2 lines) are passed to the DAC. The second timer should divide the master clock by 256 to get 44.1 kHz to update the DAC. Can the cpu run at higher frequency using the PLL and the timers run at master clock frequency? In other words, can the timers run in background starting from crystal frequency and output directly a GPIO, while the cpu works via the PLL? With the TDA1541A, since it need two lines for data in simultaneous mode (left and right simultaneously), I believe I cannot use the SPI interface with a single data line. Can I use other GPIO or what else?
  2. The PCB layout is the last thing I'm thinking now, as you said there is much road to get this project working. Usually I listen to a Steinway piano solo rather than Nina Hagen. Ok, I start considering to get the right timing from the cpu, so I need to replace the original HSE clock of the Disco board with my oscillator. The original is 8MHz, mine is 11.2896MHz. I presume that I have to change something in some headers to tell the cpu is running at a different frequency. Am I wrong? Using SPI to output bits, I can use SCLK as the bit clock for the DAC and MOSI to pump the bits in the DAC. SCLK should come from a counter fed by the master clock. But how can I clock the dac at 44.1 kHz to update? With GPIO?
  3. Thanks again for the replies. I well know this is very complex, and I'm almost ready for the challenge. I'm going to buy the STM32F4 Disco with base board and LCD expansions to start experimenting, but I'm confused about uC implementation, so I ask you more suggestions. For the critical clock at 44.1 kHz (WS/LE) I'll derive it from master clock dividing by 256 with a pair of 74LVC161, because I believe they produce less jitter than the cpu. Also for the bit clock, I can derive it from the divider (dividing by 8). As for left open the two options, discrete DAC and TDA1541A in simultaneous mode, I have to manage two different format, signed integer 2's complements and offset binary, where allx'0' represents the maximum negative value instead of zero, but I think it's not difficult to do the conversion with the cpu. So I could use the board's oscillator for the uC, since the critical timing are managed by the low jitter external master clock. Now I have to understand how synchronize the data output from the cpu with the dividers. First the uC must tell the counters to start when data are ready and to stop when whatever event happens. Second I have to pull data from the uC output, one line or two depending on the format (simultaneous mode or not). So, the cpu have to read data from SD card (SDIO) and outputs bits in a sort of buffer (SPI?) and manages the start/stop of the counter to feed the DAC. Is that right? What port/bus can I use to do the job? Thanks Andrea
  4. The TDA1541A is a difficult beast, but IMHO it's the best sounding DAC ever built. My reference is a Naim Audio CD3, it sounds wonderful, not very far from vinyl. As I said above, I have two options: the discrete dac or the 1541. In the first case, I have to feed the 595s input, as you said I could use the cpu clock, and then I have to clock the 595s to output parallel data every 256 master clock cycle. In the second case, using OB simultaneous mode, I should split data for each channel to feed simultaneously the DAC, the bit clock could be generated from the cpu, then I should provide the clock at 44.1 kHz to update the DAC. Not sure if I have to stop the bit clock of the dac after the samples are latched. If I remember correctly the TDA discards itself data exceeding 16 bit. So, back to the uC, do you suggest to use SDIO to read data from sd and SPI to feed the dac, or what else?
  5. What I meant is that my first problem is to define the right architecture of the system, since I have no experience with uC. Dac choice aside, monolithic or discrete, I would design a system rather than a dac or an SD card transport. The reason is that I'm worried about the jitter of an asynchronous system, where transport and Dac are different devices with their own master clock. SO, I would place the master clock of the entire system close to the DAC. In other words, I would pull data from the uC output (SPI?), rather than push the data from the uC. In this way I have a precise clock right to the DAC, and I'm sure each bit is latched correctly. Using 11.2896 MHz master clock, the DAC should pull the bits at that frequency from the uC, then when 32 bits are latched I have to tell the DAC to update (44.1 kHz, that means WS for I2S and LRCK fro simultaneous mode).
  6. Thanks again for the reply. About my last link: not all are audio fanatic and integralist, Scott Wurcer has an engeneer approach, not religious, he is the designer of the AD797 in Analog Devices. This is a commercial DAC using R2R ladder http://www.totaldac.com/D1-single-eng.htm The crystal oscillator was measured with a R&D FSUP by a dutch guy, attached image. About the glitch: FDS8958 has relatively high input capacitance. Could that help to reduce the glitch, smoothing the transiction? The output impedance of a ladder network should be equal to R, in my case 1K or 500 ohm. Do you think I'll have problem to adapt the amplifier input impedance? But you are absolutely right: step by step, one problem at a time. I have never worked with a uC, so this is my first problem to understand what is the best way to do the job I described. Then I could use anyway a monolithic DAC, maybe the old TDA1541A, that accepts also simultaneus mode offset binary data. So you suggest to use the crappy oscillator of the disco board for the cpu, but how can I synchronize with DAC running with a different bit clock? Best way, IMHO, is to place the master clock as close as possible to the DAC BCK and then sync back the source, the uC in this case. Is that possible using SPI or so? I found some libraries to read data from SD card, SDIO or SPI interface, so I'm confused. What interface do you suggest? When you said pumping out "pumping the bits out the spi port" do you mean also access the card via the SPI bus? Thanks Andrea
  7. Thanks for the tips. Another link: http://www.diyaudio.com/forums/vendors-bazaar/259488-reference-dac-module-discrete-r-2r-sign-magnitude-24-bit-384-khz-14.html Glitching aside, I would use 2K/1K or 1K/500R resistors and around 6V for the ladder, to get at least 2V rms at the output, to drive directly an ampli without any buffer. The DAC will be voltage output. Maybe I'm wrong, but I'm not much worried about the R2R linearity, rather I'm worried about the jitter. I thought to use an STM32F407 or 429 Discovery, with Base board and LCD expansion. I don't know if I can use my external master clock with the Discovery board. The master clock is a Clapp crystal oscillator with a single fet and a 74xx04 as the squarer. The crystal is a custom fundamental AT-cut heavily polished (ESR less than 7 ohm, Q better than 150K). A question: using SPI to pump out the bits from the uC, do you think can I slave the uC, so the DAC will act as the master for SPI? Andrea
  8. As I said above the great issue in digital to analog conversion is the jitter, when the system doesn't run totally synchronized. Do you say the only way to read data from SD card is using a FIFO? Do you think it's a "bit perfect" way? I could mask the clock of the 595s, storing each incoming bit only when the uC enables to do that.
  9. The resistors I'm planning to use are ±0.01%, 0.05ppm/°C, so I don't think to have any issue of precision and thermal stability. Also, thermal drift affects the conversion in long time, that's not a great issue. I'll use the 74LVC595, fast enough to switch at 352 kHz, but I'll don't use it to drive the ladder network, because of its relatively high RDSon. The ladder network will be drived by dual mosfet such as FDS8958 or so. I don't own the gears to measure the final precision, but on the sheet I don't see great problems. The final judge will be the ears. I'm enough sure about the digital to analog conversion, but I'm very confused about the uC. A system that don't run synchronously will be affected by some jitter, that's the great issue. That's the reason I would run alla the system synchronous, reading 1 bit from the SD card and feeding the DAC in the same clock cycle.
  10. I'm planning to use 0.02% or 0.01% resistors, so I can easily reach 16 bit precision. Modern bitstream DAC are surely cheaper, but IMHO they sound bad. I already own a SD card player that outputs I2S, used to feed a TDA1541A, an old DAC that sounds much better than the modern DAC. Now I would build an integrated system, to minimize the jitter, so I'm thinking to a uC feeding a discrete R2R DAC, using a very low phase noise master clock (-130dBc@10Hz from the carrier).
  11. I need a little help to choose the right device. I would build a digital audio player with the following characteristics: - it should read data from SD card only (up to 32GB size) - SD card will be formatted FAT32 - the root of SD card will contain folders only (named as album title/artist) - no subfolders will be allowed on SD card - each SD card folder will contain wav files only (named as title track) - only 16 bit / 44.1 kHz wav files will be allowed (CD quality) - music data should be read and managed synchronously - 6 buttons have to be managed: previous track, next track, play/pause, stop, return and enter to navigate the folders (no buttons using touch screen display) - TFT display will be managed to show album/artist, title track, time elapsed and so on (replace the buttons if touch) - data output (16 bit serial X 2 channels) should feed a r-2r discrete ladder DAC - 74XX595 logic will split the serial data to parallel to feed the ladder network - master clock should be 11.2896 MHz, shared from both DAC logic and uC, to avoid any divider - every time a single bit is ready, uC should enable the 595 to store it (595 clock enabled from uC in sync with master clock) - every time 16 bit for 2 channels are read, uC in sync with master clock should enable the 595s to output parallel data to update the ladder network Practically, file system and wav headers aside, using 11.2896 MHz master clock for all the system, I have to start reading 4 bytes from the SD card (1 left + 1 right samples), then I should pass each single bit synchronously to 4 * 74XX595. The clock of the 595 to store data should be enabled either from the master clock and the uC (data ready to store). After the 32th bit is stored in the last 595, uC should enable the master clock to tell all the 595s to output parallel data to update the ladder network. Finally the clock of all the 595s should be stopped for 224 cycles, and no data should be read from the SD card. Now the program has to read next 4 bytes, until the end of the wav file. In the meantime I have to manage the TFT display and interrupt from the user buttons or touch screen What device do you suggest to do all the above job? STM32 M4? Can I run all the system at the same master clock (11.2896 MHz)? Can I read and manage data synchronously from the SD card? . Thanks Andrea
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