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Kotdnz

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  1. Kotdnz

    SSI and LM4F120XL

    No. It's not my situation. I migrate to stm32 platform.
  2. Kotdnz

    SSI and LM4F120XL

    You right. It's more elegant method, but doesn't resolve non worked SPI It's force me migrate to other board
  3. Kotdnz

    SSI and LM4F120XL

    We have only 6 bits and maximum possible is 0x3F. SPI module working fine - i connect it to arduino and all working fine. It's inside stellaris problem.
  4. Kotdnz

    SSI and LM4F120XL

    0x7e = 0111 1110 For example for read register 0x14 value i need to send 0x14 = 0001 0100 shift left << 1 0010 1000 mask (AND) with 0111 1110 result is 0010 1000 and last - set first bit to 1 OR with 0x80 1000 0000 we have 1010 1000 <=> mask 1XXXXXX0 it's 0xA8 Something wrong? oops.... i'm first time read this Where is possible read more detailed info about this ?
  5. Kotdnz

    SSI and LM4F120XL

    // Address format:1XXXXXX0 it's a reason why we shift left, set last bit to 0, set first bit 1.
  6. Kotdnz

    SSI and LM4F120XL

    Today i try next steps: 1. Switch off all other functions. 2. Reconnect and reconfigure to pins SSI0_BASE 3. Correct read function to SSIDataPut(OUR_SSI, ((addr<<1)&0x7E) | 0x80); 4. Change SSI speed to 4'000'000 5a. WIth SSI_FRF_MOTO_MODE_0 i receive 5b. With SSI_FRF_MOTO_MODE_3 Result - have nothing
  7. Kotdnz

    SSI and LM4F120XL

    Lyon, Thank you, i will check. On RTC - only simple watch for actual date/time in notifications - it's a home secure system.
  8. Kotdnz

    SSI and LM4F120XL

    Oops... Thank you - it's look like solution. May be i release RTC by simple timer with unix_time. Is it possible count ticks in timer interrupt based on 32KHz RT crystall? Thanks again, hope returned to me.
  9. Kotdnz

    SSI and LM4F120XL

    Hi, I check is this clock setup working by invoke SysCtlClockGet and return 80'000'000. My device can run up to 10MHz, so i can use faster SPI. Are you mean change to mode 3 - Motorola code? So final SPI config may look like SSIConfigSetExpClk(SSI3_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_3, SSI_MODE_MASTER, 5000000, 8); About RTC - when we told about clock speed and they effect to system i initialize RTC via next code: //Realtime Clock and hibernate ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_HIBERNATE); // clear data HWREG(HIB_CTL) |= HIB_CTL_CLK32EN | HIB_CTL_OSCDRV; // Delay for the maximum crystal oscillator start-up time of 1500ms ROM_SysCtlDelay (1500 * (ROM_SysCtlClockGet() / 3 / 1000)); ROM_HibernateRTCSet (0); ROM_HibernateEnableExpClk(ROM_SysCtlClockGet()); //must be called first have a look page at 458 (spms294e.pdf) HibernateClockConfig(HIBERNATE_OSC_DISABLE | HIBERNATE_OSC_HIGHDRIVE); //select the external crystal with 24pF filter capacitor (for launchpad lm4f120xl) HibernateClockSelect(HIBERNATE_CLOCK_SEL_RAW); //select the raw output of the 32khz crystal HibernateRTCTrimSet(0x7FFF); // must be called. if you don't set manually the trim register, the counter counts too fast or too slow have a look at page 462 (spsm294e.pdf) HibernateGPIORetentionEnable(); ROM_HibernateWakeSet(HIBERNATE_WAKE_PIN); ROM_SysCtlDelay(6400); //necessary, without this rtc won't work. don't really know why ROM_HibernateRTCEnable();
  10. Kotdnz

    SSI and LM4F120XL

    I already use PinMux. My target is receive reply: is trouble with SSI is a well know stallaris problem (or community know about defected series in the market) or it's only my private situation and require only optimize configuration. In errata i found: “Freescale SPI Mode at low SSIClk frequencies can yield data corruption” Description: Data transmitted by the SPI slave may be corrupted when using Freescale SPI Mode 0 at an SSIClk frequency between 0.5 MHz to 1.1 MHz and a system clock frequency of 33 MHz or lower. Workaround: Operate the Freescale SPI Mode 0 at an SSIClk frequency above 1.1 MHz and use a system clock frequency above 33 MHz or use a different mode. P.S. my system clock speed is 80MHz SysCtlClockSet(SYSCTL_USE_PLL | SYSCTL_SYSDIV_2_5 | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ); and i use RTC.
  11. Kotdnz

    SSI and LM4F120XL

    Lyon, My question about SPI. Doesn't mater what rc522 reply. Important - on command SSIDataPut(SSI3_BASE, 0xBA); logic analyzer show, that stellaris send ZERO.
  12. Kotdnz

    SSI and LM4F120XL

    You right correct sentence ((addr<<1)&0x7E) | 0x80 but i try send directly SSIDataPut(SSI3_BASE, 0xBA); with same result
  13. Kotdnz

    SSI and LM4F120XL

    Yes, sure IAR Workbench 6 Project options windows
  14. Kotdnz

    SSI and LM4F120XL

    Hello, Board LM4F120XL (LM4F120H5QR) need Guru help with SPI. Configuration: ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3); ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); ROM_GPIOPinConfigure(GPIO_PD3_SSI3TX); GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_3); ROM_GPIOPinConfigure(GPIO_PD2_SSI3RX); GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_2); ROM_GPIOPinConfigure(GPIO_PD0_SSI3CLK); GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_0); ROM_GPIOPinConfigure(GPIO_PD1_SSI3FSS); GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_1); SSIConfigSetExpClk(SSI3_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, SysCtlClockGet()/80, 8); SSIEnable(SSI3_BASE); // clear FIFO buffer unsigned long pui32DataRx; while(SSIDataGetNonBlocking(SSI3_BASE, &pui32DataRx)) { } And next function is read SPI: static unsigned char Read_MFRC522(unsigned char addr) { uint32_t val; RF_Activate(); // Address format:1XXXXXX0 val = ( addr << 1 ) & 0x80 ; SSIDataPut(OUR_SSI, val); while(SSIBusy(OUR_SSI)); SSIDataGet(OUR_SSI, &val); while(SSIBusy(OUR_SSI)); SSIDataPut(OUR_SSI, 0x00); while(SSIBusy(OUR_SSI)); SSIDataGet(OUR_SSI, &val); while(SSIBusy(OUR_SSI)); RF_Deactivate(); return val; } due to datasheet when read device register 0x14 i must receive value 0x80, but by logic analyzer show next My board send nothing. But CS switched, CLK working, but on TX nothing. May be i forget something? My friend say it's defected IC. Before SSI3 i try to use SSI0 base with same pure result.
  15. I adopt your code in clear C code IAR project by adding wiring.h In my configuration i use pin PB5 void Init_rcswitch(void){ ROM_GPIOPinTypeGPIOInput(GPIO_PORTB_BASE, GPIO_PIN_5); // configure PIN ROM_GPIOIntTypeSet(GPIO_PORTB_BASE, GPIO_PIN_5, GPIO_BOTH_EDGES); // invoke on any changes ROM_GPIOPinIntEnable(GPIO_PORTB_BASE, GPIO_PIN_5); // PB5 IntEnable(INT_GPIOB); //sets the interrupt controller to interrupt on GPIO port B } // our isr handle void recv_PortPin(void){ ROM_GPIOPinIntClear(GPIO_PORTB_BASE, GPIO_PIN_5); .... last string is important
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