tonyp12

As all gio registers start with port and then OUT, IN, IE etc, example: P1OUT, with some macro word scrambling you can do this: #define read & // words for common gpio interaction #define clear &= ~ #define set |= #define toggle ^= #define Button1(y,x) (P1 ##x y BIT0) // PORT and PIN (ignore the ##x y) #define BlueLED(y,x) (P2 ##x y BIT5) To use them: BlueLED(set,DIR); BlueLED(clear,OUT); Button1(clear,DIR); // a input Button1(set,OUT); // pull-up resistor Button1(set,REN);

#include "msp430.h" #define UART_RX BIT1 #define UART_TX BIT2 #define UART_PORT(x) (P1 ##x) #define softintvec 0xC0004210 // start of flash + opcode for BR void bootloader_reset(void); void TXdata(char* pnt, int len); void bootloader_USCIAB0TX(void); void bootloader_flasherase(void); __interrupt void bootloaderRX_ISR(void); //-------------------- define structures -------------------- struct jumpstruct { const unsigned long branch[16]; const unsigned int bsl; const unsigned long* vector[16]; }; //-------------------- declare strings ---------------------- #pragma location = "BOO

The idea is that any new firmware does not include the upper 512bytes of Flash, but as IRQ vectors will change with new firmware but is now part of the firmware-block as compiler Intvec have been moved -512 bytes down. If you put your custom Loader in the upper 512bytes too and as you never erase this block, much less chance of bricking. I guess opcode for BR could change from msp family? but this does work on a G2553. ?CCS could use pragma location if it can not handle @ Not all vectors are available or used, so you should fill them with random value instead for the BSL password if yo

I think this is the smallest I can get it if you always use 2,4 or 8 task. ?I did a second fibo, that task sure need a larger stack, it crashes if I don't give it 70 words each __regvar __no_init unsigned int taskrun @ __R4; ?... stackpnt[i] = (unsigned int) (multistack-12); // PC+SR+11 dummy push? R4 is no longer pushed ?... taskrun = 0; ... asm (" mov SP,stackpnt(R4)"); asm (" incd R4"); asm (" bic #-8,R4"); asm (" mov stackpnt(R4),SP"); RESULT 7 WORDS 1205 push.w R5 ; last push 4184 0200 mov.w SP,0x200(R4) 5324 incd.w R4 C034 FFF8 bic

>cmp r6, r5 ?I don't see where R6 is set? I could reserve R4 as a __regvar and use it as the taskstackpnt, compiler probably could then do the switching in 6 words plus one less push/pull?. But if tasks run out of regs it will use the stack, so that is a trade off but probably only happens with function-calls that pass a couple of longs.

... 1204 push.w R4 ; last push 410F mov.w SP,R15 ; it does not remove it due to volatile 421E 0200 mov.w &taskrun,R14 418E 0000 mov.w SP,0x0(R14) 532E incd.w R14 903E 0208 cmp.w #0x208,R14 2002 jne 0xC0CE 403E 0202 mov.w #0x202,R14 4E82 0200 mov.w R14,&taskrun 4E0F mov.w R14,R15 ; another wasted due to volatile 4E21 mov.w @R14,SP 4134 pop.w R4 ; first pop ... IAR is the Kin

Code is free for non-commercial use, for commerical use a negotiated donation amount. ?Though commercial use will be after I added more features. ?I was able to trim it down to 13words, though as SP is volatile it wastes two words moving SP to R15 twice that is never used (in high optimization) = 15 words I have not tested this yet *taskrun = __get_SP_register(); if (++taskrun == taskstackpnt+tasks) taskrun = taskstackpnt; __set_SP_register(*taskrun); and in main.c change to int* taskrun = taskstackpnt;

preemptive means that the code (e.g.each task that is pretty much its own main.c) does not know it is sharing a single mcu core. it does not need to say "i take a pause now so next task can go on", you can even run two instances of the same task (though not really useful) A higher power takes over and switch tasks. Sure there is stuff to add like system_sleep and priority and maybe even new task and end task etc. I plan to show how to use a 512Hz mems osc to NMI pin, so task switching can not be overridden by (maybe mistakenly) disabling GIE. ?wiki: Preemptive multitasking wiki: Cooper

?{28}; is the same thing as {28,0,0} and 28 was just random number to show something so if you forget to fill in all stack sizes for each task I will give you 24 words (48bytes) A minimum should be 14 words if your task don't use the stack at all. -26, as I cast the address to (int) it's now a byte space referenced If I wrapped it first (int) (multistack-13); it will be word referenced as it is a int pointer, probably should wrap it for next time, ?So I'm just adjusting the stack pointer to include the PC,SR and the 12 pop's it will see on first entry (only done for task2+) That is

I may replace the c code in isr with asm if I can not make changes to get it optimized so it only uses 8 words, now it uses 19 words, but making stuff (int*) instead of array[char value] I think that will get it down to 12 at least. If all asm of course there is no need for __raw if you compiler don't support it. btw the asm ("br &taskpnt") can be done in C by: taskpnt[0](); but it does a call and that wastes a stackword for return address. So unless you want task1 to have an option to exit and return to that spot in main, a exit in task1 now would use the return address from the or

You're right, that is room for 16 multi-stacks!! Run that msp at 16Mhz, intervals will now be 2ms and you have something powerful. ?IRQ's can handle the real-time stuff and just make sure you always code with the thoughts that code can get on hold at any time (though temporary disable WDTIE will give you a lock) ?I just selected 1K+ and did not see that some had even more. http://www.ti.com/lsds/ti/microcontrollers_16-bit_32-bit/msp/ultra-low_power/msp430g2x_i2x/products.page#p1219=1;4

a ISR always have way to trick the RETI by modifying the SR values on stack. I trick the RETI with a different stack location , task 1 have a stack as normal as first entry in to ISR the PC,SR and R15-R4 are push'ed ? But for the other tasks I have to preset the PC and SR in the "fake" stack for its first entry in and also offset the stack pointer as it will see 12 pop's the first time without seeing the 12 push'es yet. I plan to add system_delay() so task can asked to be put on hold, though it will be hard to calculate a actual time if other tasks also do that at the same time. mayb

Tested on G2553 Launchpad with IAR, I recommend G2955 with 1K RAM if you want more than 3 task #include "msp430.h" #include "common.h" //=========================(C) Tony Philipsson 2016 ======================= funcpnt const taskpnt[]={ task1, task2, task3, // <- PUT YOUR TASKS HERE }; const int stacksize[tasks] = {28}; // a blank value defaults to 24 stack words //========================================================================= int taskstackpnt[tasks]; unsigned int taskdelay[tasks]; char taskrun; int main( void ) { WDTCTL = WDTPW + WDTHOLD;

If you look at the disassembly, you can see that is set R1 to either 1 or 0 every time before it writes to the bitband region. That must waste double the time, strange that ARM4 don't have built in BME, so you can use XOR etc on the bitband region. (eg Decorated store operations) Just a quick dirty test shows that if you can store 1 to R1 and 0 to R2 you double the rate, if the hardware can keep up that is. I tried to declare two uint8_t inside the function so compiler reserved the values in R1 and R2 but no go, it used the stack. So a BITBAND_PERI Toggle Function needs to be created that