32xan

Ugh.. the check for OFIFG is missing in my code; thanks to `https://forum.43oh.com/topic/1943-comprehensive-dco-calibration/`

I'm failing to see why I could not clock the CPU of the msp430g2452 for 32KHz wath crystal. I'm observing the same behavior from two different launchpad boards with soldered 32Khz crystal (one tiny yellow crystal that came with the kit and cylinder bigger one); and with several different msp430g2452. I'm observing the 32KHz square on P1.0 when it set to output the ACLK. Seems that the MCLK is always clocked from DCO regardless of the SELM_[0-3] I'm trying to push to BCSCTL2. I'm checking P2.1 output as it is software toggled in endless loop; it is 20 times slower than MCLK.

> There is nothing attached to the reset pin. Always connect a pull-up resistor (47k?) and a pull-down capacitor (2.2nF) to reset ( that's form roadrunner's post)

I'm working in project where few MSP430G2* and i2c-ready ADC/DAC are doing I2C communication. While the DAC/ADC have proper open-drain SDA/SCL, I don't find a way to operate MSP430G2* with open-drain output while software bit-banging ports P1.6 and P1.7. So, did I miss some details in SLAS722/SLAU144 and msp430g2 could operate honest open-drain (as in opposite to manipulate P1DIR.[67] while keeping P1OUT.[67] low, that how I'm doing now)? Thanks,

Have you tried avnetexpress.com?

Capacitor is missing on the Reset pin of MSP430. Also, the TLC5916 has min 0.6V on the Vo for 26 mA (from datasheet). With only 0.4V on the Vo of the TLC5914 I kind of curios how stable/predictable it would sink 10mA (or whatever you would programm TLC5914 to sink)?