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oPossum

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Everything posted by oPossum

  1. This code will print a 64 bit unsigned integer in 5 characters using 3 significant digits and and an SI prefix. Several revisions are shown beginning with the obvious implementation and then optimizing it to improve speed and decrease code size. Compilers used are TI 4.4.4 and GCC 4.9.1 Test hardware is the F5529 Launchpad running at the default clock of 1.016 MHz. The general strategy of the code is: - Count the number of digits in the decimal representation - Divide the value to reduce it to 3 digits. - Print the 3 digits with proper formatting and SI prefix. - Handle the special cas
  2. It is possible to do thermal pads without a reflow oven or hot air.
  3. Have you ever seen any frames with more than 16 packets? Maybe the lower nibble of the first byte is the packet sequence and the upper nibble can be ignored.
  4. Checking for proper sequence... (only changed code shown) struct Fastpacket { unsigned char *bufferEnd; // End of buffer + 1 unsigned char *bufferPos; // Next char goes here unsigned char seq; // Next char in sequence }; struct Fastpacket *newFastpacket(size_t const size){ // Allocate enough memory for the structure and the buffer struct Fastpacket *retVal = malloc(sizeof(struct Fastpacket) + (size * sizeof(unsigned char))); if(retVal) { // Buffer begins after the structure retVal->bufferPos = (unsigned char *)(retVal + 1); re
  5. Nothing wrong with what you have written. If you want it a little faster and smaller with a little less memory fragmentation, here is some optimized code... struct Fastpacket { unsigned char *bufferEnd; // End of buffer + 1 unsigned char *bufferPos; // Next char goes here }; struct Fastpacket *newFastpacket(size_t const size){ // Allocate enough memory for the structure and the buffer struct Fastpacket *retVal = malloc(sizeof(struct Fastpacket) + (size * sizeof(unsigned char))); if(retVal) { // Buffer begins after the structure retVal->bufferPos =
  6. unsigned int pgn = ((pgn_field.bytes.byte4 >> 4) << 16) + (pgn_field.bytes.byte3 << 8) + (pgn_field.bytes.byte2); should probably be unsigned int pgn = ((pgn_field.bytes.byte4 & 0x1F) << 16) | (pgn_field.bytes.byte3 << 8) | (pgn_field.bytes.byte2);
  7. Looks like this is the code that does the printing in your candump example... void sprint_long_canframe(char *buf , struct can_frame *cf, int view) { /* documentation see lib.h */ int i, j, dlen, offset; int dlc = (cf->can_dlc > 8)? 8 : cf->can_dlc; if (cf->can_id & CAN_ERR_FLAG) { sprintf(buf, "%8X ", cf->can_id & (CAN_ERR_MASK|CAN_ERR_FLAG)); offset = 10; } else if (cf->can_id & CAN_EFF_FLAG) { sprintf(buf, "%8X ", cf->can_id & CAN_EFF_MASK); offset = 10; } else { sprintf(buf, "%3X ", cf->can_id & CAN_SFF_MASK); offset
  8. Bit 31 of can_frame.can_id indicates if an 11 or 29 bit address is used. It is probably being masked by the candump program because it is not actually part of the address. It would be nice if the candump program used 3 or 8 hex digits to indicate the address size in use. Using a stream (socket) for a block based protocol seems like a bad idea. Much that can go wrong.
  9. I have recovered from alcoholism, but my eyesight has become worse. I have never said this, and never will. I use Linux, OS-X, and Windows. They are all very frustrating at times and all lack features I would like them to have. I was just pointing out that Windows and OS-X both support disk images without any additional software. They both allow command line or GUI tools to be used. You are correct that it is not exactly the same as using dd. The Windows Virtual Hard Drive (vhd) and OS-X Disk Image (dmg) go beyond simple byte-for-byte copies of a chunk of media. The GUI tools wi
  10. Many of them are available with cygwin. Windows goes far beyond these simple utils with powershell. Trivial. You can use command line or GUI to make images, mount them, and even boot them. https://technet.microsoft.com/en-us/library/gg318052(v=ws.10).aspx Sharing them over the network can also be done with GUI or command line. Same for OS-X using Disk Utility as a GUI or command line tool.
  11. In Windows there are several timing parameters for async serial (COM) ports that are configured with the SetCommTimeouts() API call. https://msdn.microsoft.com/en-us/library/windows/desktop/aa363437 https://msdn.microsoft.com/en-us/library/windows/desktop/aa363190 These settings in combination with the buffer sizes use for tx/rx can have a significant impact on latency. This latency is in addition to that of the USB to serial hardware. I suspect that it is not possible to modify this stuff when using LabView. Not sure about C#. It is, of course, possible to adjust all this when us
  12. When using the G2553 hardware UART with a rev 1.4 or earlier launchpad the tx and rx pins have to be connected in an X configuration. http://forum.43oh.com/topic/1261-a-useful-dongle-for-g2553s-on-the-launchpad/
  13. It does not use timers or interrupts. All functions return immediately - there is no polling. Clock stretching is *not* supported.
  14. Give software IIC a try. The hardware IIC on MSP430 is poorly designed and hard to use. It is the only peripheral on MSP430 that I never use. I avoid it. http://forum.43oh.com/topic/2358-software-iic-master-in-c-c-class-and-c-template/
  15. The BSL uses the timer A to do 'software' UART so it can precisely adjust to the bitrate of the host while running from an uncalibrated internal clock.
  16. It's close. Can be made more accurate... Set the oscillator to one of the calibrated values. DCOCTL = 0; BCSCTL1 = CALBC1_1MHZ; DCOCTL = CALDCO_1MHZ; Set the max count to N - 1 TA0CCR0 = (1000000 / 38000) - 1; TA0CCR1 = TA0CCR0 >> 1;
  17. This code quickly determines if a date is within daylight savings time (DST). A companion function adjusts the date and time if necessary. There are many ways to determine if a date is within DST. This code begins by checking large time spans (months) and works down to shorter time spans (hours) as necessary. So for most of the year the decision is made very quickly. The worst cases occur on the days of the transition. BCD representation is used for compatibility with most hardware RTC chips. The day of week (T_RTC.dow) must be set properly for this code to work. Day of week is a value
  18. 2.2k is a reasonable value for 3.3V IIC. Both SDA and SCL require resistors because they are both open drain (pulled low only). The SCL line is open drain to allow a slave to do clock stretching - a rarely used feature.
  19. Those old 8 bit ECUs have support chips that help with all the timing critical stuff. With a G2553 you have a faster CPU, but only wo very basic timers. Each can only do two full featured compare outputs, so your need for three outputs is just beyond what it can easily do. The F5529 has a timer A with five outputs, and a timer B with 7 outputs, so it is much better able to do what you need.
  20. CH340 is the worst of them all. I have never been able to get one to work on a current version of Windows.
  21. No, not due to sales. Sales are fine at Parallax. They have been releasing a FPGA bitstream for the Propeller 2 that has been under development. The community really like being able to test a next gen chip before it became available. The release of a VHDL and bitstream for a Propeller 1 workalike will in no way harm sales of the Propeller chip. The FPGA is much more expensive then a propeller chip, and it would not be cost effective for a competitor to have an ASIC made. It is simply something they are doing for a few in the community that can hack away at the VHDL and do cool stuff.
  22. char *p = text; char *q; char *str; while ((str = strtok_r(p, ",", &q)) != NULL) // delimiter is comma { p = NULL; Serial.println(str); delay(500); }
  23. The FTDI is capable of jitter free operation at 3,000,000 / N bps. It can use fractional division for operation at more bit rates, but that causes some jitter, so I don't recommend it. It has no special knowledge of 'standard' bit rates like some other chips - it is a simple divider. So the highest reliable bit rates for the FTDI chips are 1.5M, 1M, 750k, 600k, 500k, etc...
  24. Get a FDTI board. Just do it. You will find many uses for it and soon have several. 6 channel MSP430 logic analyzer with 256k sample memory: http://forum.43oh.com/topic/2480-6-channel-logic-analyzer/
  25. The timer info is listed a few placed in various ways. I like to look at the tables in the Port Schematics section starting on page 43. That shows all possible uses for all the pins. It is possible to do PWM on CCR0 with some software ISR assistance. This method is not supported by Energia - it only uses strictly hardware PWM. http://forum.43oh.com/topic/5619-pwm-using-timer-output-toggle-mode/
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