-
Content Count
925 -
Joined
-
Last visited
-
Days Won
103
oPossum last won the day on February 2 2021
oPossum had the most liked content!
About oPossum
-
Rank
Poke me with a Stick
Profile Information
-
Gender
Not Telling
-
Location
Michigan, USA
Recent Profile Visitors
The recent visitors block is disabled and is not being shown to other users.
-
There are 5 vectors in that table
-
http://forum.43oh.com/topic/2482-3-way-50x50mm-proto-board/ http://forum.43oh.com/topic/2481-launchpad-mini-revision-3/
-
Free shipping until 9/18/2016.
-
They have to compete with ARM M0+, M3, M4 and M7; plus many 4 and 8 bit parts from Asia. There is no lack of competition. TI has hurt themselves with poor management of their low end ARM chips (Stellaris, Tiva, MSP432). MSP430 will remain a great low power choice for quite some time.
-
A variation of the RTTL player that adds a simple envelope to each note. Some in assembly & C: MIDI driven: http://forum.43oh.com/topic/810-fraunchpad-poly-synth/ This has a bug that causes only half of the sine wave to be used. Look carefully at the 'scope and you will see it. Table driven: This has a bug that causes the frequency to be a bit off. Don't remember if I fixed the posted code. http://forum.43oh.com/topic/1729-fraunchpad-synth-still-alive/
-
Wait for transmission of all bits to complete before latching the outputs void WriteData(unsigned char data) //SPI { UCB0TXBUF = data; // Transmit character while(UCB0STAT & UCBUSY); // Wait for all bits to finish P2OUT |= LATCH_BIT; // Pulse latch P2OUT &= ~LATCH_BIT; }
-
Flash memory can be damaged by writes? (and related things)
oPossum replied to ElTita's topic in Energia - MSP
Flash will wear out after being erased and written many times. As a practical matter you will have to keep the pointer to the flash in RAM. This would be a good application for one of the FRAM MSP430s. They have essentially unlimited write endurance. -
Intel opens up the embedded MCU on the EDISON board
oPossum replied to abecedarian's topic in Other Microcontrollers
Older versions did. The first Intel Macs where Core Duo, so they could not run 64 bit. The later versions of MacOS are a mix of 32 and 64 bit. -
Code Composer Studio upgrades are now free (revised)
oPossum replied to oPossum's topic in Compilers and IDEs
Ahh. That link has a better explanation. It is still necessary to purchase CCS, but all upgrades are now free. Same model as Windows 10. Buy once and upgrade forever until corporate policy changes. -
Edit: Upgrades to CCS are now free, not the entire product. An initial purchase is still required. Just got this email from TI:
-
They are two distinct interrupts, you do not have to enable both. The TAIE bit in TACTL enables an interrupt that occurs when the timer reaches 0. The CCIE bit in the TACCTLx registers enables an interrupt that occurs on a match between the compare register or a capture event. All these interrupt enable bits are completely independent of each other. Enable only those that you are using and have written an ISR for. The only other interrupt that has to be enabled is the global interrupt flag in the status register. That can be enabled with _enable_interrupts() or a few other
-
If the TA0CTL line you posted isn't actually commented out, then your code may be stuck in the other Timer A interrupt (TIMER0_A1_VECTOR). That interrupt requires reading TA0IV to clear the flag. If you don't read TA0IV, it will get stuck with that ISR repeating endlessly. The fix is to remove TAIE from that line. TA0CCTL0 |= CCIE; // enable interrupt TA0CTL |= (TASSEL_2 + MC_1 + TAIE); // start timer, enable interrupts
-
// Timer A0 interrupt service routine #pragma vector=TIMER0_A0_VECTOR __interrupt void Timer_A (void) { } // <<<---- missing closing brace <<<---- // Port 1 interrupt service routine #pragma vector=PORT1_VECTOR __interrupt void Port_1(void) { P2OUT ^= (BYPASS & STATUS_LED); // MAKE BYPASS AND LED HIGH P2IFG &= ~POSITION; // RESET INT UPON POSITION HIGH }