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Found 7 results

  1. Hi, I'm implementing an application for CC3200MOD in Energia 1.6.10E18 environment in which host MCU (Atmel AT76C114) sends jpeg image data (size varies from 1MB to 3MB) over SPI to CC3200MOD which then sends it over WiFi to PC. So Atmel acts as SPI master and CC3200MOD SPI slave. The bottleneck is SPI receive rate in CC3200MOD end. I need to configure host MCU SPI clock to 10.5MHz in order to receive correct data on CC3200MOD. With higher clock rate the data gets corrupted. When receiving valid data the transfer rate is 0.17 MBps. This is way too low for our purposes. I have understood that by using SPI DMA one could receive higher transfer rate. Are there any SPI DMA examples available for SPI slave receive in Energia environment? Does SPI DMA work on SPI slave when SPI master sends data continuously or does it require changes also for the sending procedure from SPI master? Thanks, Yuzzie
  2. Hi, I'm a bit new to this... I'm wanting to improve the performance of the SPI, I understand that using DMA is the best solution. Are their any example of SPI with DMA? Currently without DMA, I have the SPI setup to send 1 byte at a time with: SPI_transmitData(LCD_EUSCI_MODULE, data); What I want to do is change this so I can fill a buffer with bytes, then say Send. Once thats finished sending I want to fill the buffer again and send the next set of bytes. I tried to use this code although it appears to hang at the last line! DMA_enableModule(); DMA_setControlBase(m_controlTable); DMA_assignChannel(DMA_CH0_EUSCIB0TX0); DMA_disableChannelAttribute(DMA_CH0_EUSCIB0TX0, UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK); DMA_setChannelControl(UDMA_PRI_SELECT | DMA_CH0_EUSCIB0TX0, UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_8 | UDMA_ARB_8); DMA_setChannelTransfer(UDMA_PRI_SELECT | DMA_CH0_EUSCIB0TX0, UDMA_MODE_BASIC, m_data_array, (void*)SPI_getTransmitBufferAddressForDMA(EUSCI_B0_MODULE), 1024); DMA_assignInterrupt(DMA_INT1, 0); Interrupt_enableInterrupt(INT_DMA_INT1); ? I was planning to use the code above by filling the buffer "m_data_array" then calling DMA_enableChannel(0); although this didn't work. How do i know when the buffer has been transmitted?
  3. Here is some code to drive ws281x strips using DMA driven SPI for the msp430f5529. I hadn't seen any example code showing how to use DMA and SPI. The example also provides some code that shows how to use inline asm that will work with both msp430-gcc and msp430-elf-gcc. The code below was tested with a ws2811 strip and msp430-elf-gcc. https://gist.github.com/RickKimball/9761b8f5a89d46a53939 -rick
  4. Does anyone have any good sources of performance information for the PL230 uDMA used in Tiva and CC3200 MCUs (or any MCU using the same DMA controller)? I'm used to using MSP430 DMA which is quite clearly specified. Each transfer spends two MCLK cycles accessing the bus (which halts the CPU), plus an extra two cycles each time it's triggered. The synchronisation time required to wake up from various low power modes is also given. The Tiva and CC3200 TRMs don't give any details of this type. I'd like to know how many cycles each transfer takes in the best case, with no contention, arbitration or wait states involved. I'd also be interested to know how achieveable that is in the real world. Additionally I'd like to know whether all those cycles involve bus access. As I understand it the Tiva DMA can only access the SRAM when the CPU isn't using it, so I'm wondering how easy it is to run the DMA and CPU in parallel without the DMA being starved of SRAM access. I've looked at ARM's documentation for the PL230 and it's not much better. The only timing information appears to be in the signal timing diagrams: This diagram suggests it takes 7 cycles per transfer, but the description in the document implies it's set up to arbitrate after each transfer. Perhaps it goes faster if arbitration is less frequent? This one shows four cycles per transfer using waitonreq and arbitration every two transfers. That's two differences to the configuration in the previous diagram, so I don't know which change is responsible for the different timing. Also both diagrams have unexplained idle periods at the start, and the waitonreq diagram has one at the end too. Any first-hand info or recommended reading on this would be much appreciated. Thanks! EDIT: I found an interesting appnote from Silicon Labs for their Gecko line (AN0013). It gives timing for a single transfer from ADC to SRAM and explains how arbitration rate affects the flow through the DMA state machine. Still, it leaves a lot of questions unanswered. How long do about transfers to/from other peripherals and SRAM->SRAM transfers take? Also it's not clear whether the timings given are purely due to the DMA controller itself, or the specific slave devices it's communicating with (ie does this information transfer across to other MCUs using the same controller).
  5. https://github.com/jmagnuson/fatfs-tiva-cm4f/blob/master/src/third_party/fatfs/port/mmc-tiva-cm4f.c It's still a work in progress, but should be a working drop-in replacement for the MMC driver TI provides. I've only done minimal testing on it thus far, so any corrections or improvements would be greatly appreciated!
  6. Hi, i would like to move data from ADC12MEM0 from its memory location to a choosen mamoery location by the means of DMA. the ADC is working correctly. Here it follows DMA configuration : __data16_write_addr((unsigned short) &DMA0SA,(unsigned long) ADC_MEM_0_ADDRESS); //SHOULD BE ADC12MEM0 // Source single address __data16_write_addr((unsigned short) &DMA0DA,(unsigned long) IMAGE_START_ADDRESS); // Destination single address DMACTL0 =DMA0TSEL_26; //DMA Trigger Assignments:26==ADC12 end of conversion DMA0SZ =12544; // Block size DMA0CTL = DMADT_4 | DMASRCINCR_0 | DMADSTINCR_3 | DMADSTBYTE |DMASRCBYTE; // Rpt, inc DMA0CTL |= DMAEN; // Enable DMA0 i expect the DMA to transfer 12544 byte at once, and at each ADCcycle i expect DMA0SZ to decrease of one unit. But looking at DMA0SZ durign the dug it seems like it doen't even decreases at any ADC cycle despite what it is written in the datasheet SLAU367b "DMAxSZ register decrements with each word or byte transfer." any tips on what i'm missing? thx in advance irene